gwj / at91sam9263 · Commits

Commit 46f42f2940bc6912b85d616ad6c8fcfe024153f6

Authored by blueswir1
1 parent d4abd567

Update from binutils 2.17 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5543 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 627 additions and 579 deletions
sparc-dis.c
  View file @46f42f2
@@ -5,23 +5,28 @@ @@ -5,23 +5,28 @@
5 5
6 /* include/opcode/sparc.h */ 6 /* include/opcode/sparc.h */
7 7
8 -/* Print SPARC instructions.  
9 - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,  
10 - 2000, 2002 Free Software Foundation, Inc. 8 +/* Definitions for opcode table for the sparc.
  9 + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
  10 + 2003, 2005 Free Software Foundation, Inc.
  11 +
  12 + This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
  13 + the GNU Binutils.
  14 +
  15 + GAS/GDB is free software; you can redistribute it and/or modify
  16 + it under the terms of the GNU General Public License as published by
  17 + the Free Software Foundation; either version 2, or (at your option)
  18 + any later version.
11 19
12 -This program is free software; you can redistribute it and/or modify  
13 -it under the terms of the GNU General Public License as published by  
14 -the Free Software Foundation; either version 2 of the License, or  
15 -(at your option) any later version. 20 + GAS/GDB is distributed in the hope that it will be useful,
  21 + but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23 + GNU General Public License for more details.
16 24
17 -This program is distributed in the hope that it will be useful,  
18 -but WITHOUT ANY WARRANTY; without even the implied warranty of  
19 -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the  
20 -GNU General Public License for more details. 25 + You should have received a copy of the GNU General Public License
  26 + along with GAS or GDB; see the file COPYING. If not, write to
  27 + the Free Software Foundation, 51 Franklin Street - Fifth Floor,
  28 + Boston, MA 02110-1301, USA. */
21 29
22 -You should have received a copy of the GNU General Public License  
23 -along with this program; if not, write to the Free Software  
24 -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */  
25 #include <stdlib.h> 30 #include <stdlib.h>
26 #include "dis-asm.h" 31 #include "dis-asm.h"
27 32
@@ -40,17 +45,18 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ @@ -40,17 +45,18 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
40 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 45 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
41 Don't change this without updating sparc-opc.c. */ 46 Don't change this without updating sparc-opc.c. */
42 47
43 -enum sparc_opcode_arch_val { 48 +enum sparc_opcode_arch_val
  49 +{
44 SPARC_OPCODE_ARCH_V6 = 0, 50 SPARC_OPCODE_ARCH_V6 = 0,
45 SPARC_OPCODE_ARCH_V7, 51 SPARC_OPCODE_ARCH_V7,
46 SPARC_OPCODE_ARCH_V8, 52 SPARC_OPCODE_ARCH_V8,
47 SPARC_OPCODE_ARCH_SPARCLET, 53 SPARC_OPCODE_ARCH_SPARCLET,
48 SPARC_OPCODE_ARCH_SPARCLITE, 54 SPARC_OPCODE_ARCH_SPARCLITE,
49 - /* v9 variants must appear last */ 55 + /* V9 variants must appear last. */
50 SPARC_OPCODE_ARCH_V9, 56 SPARC_OPCODE_ARCH_V9,
51 - SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */  
52 - SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */  
53 - SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ 57 + SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
  58 + SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
  59 + SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
54 }; 60 };
55 61
56 /* The highest architecture in the table. */ 62 /* The highest architecture in the table. */
@@ -65,14 +71,15 @@ enum sparc_opcode_arch_val { @@ -65,14 +71,15 @@ enum sparc_opcode_arch_val {
65 71
66 /* Table of cpu variants. */ 72 /* Table of cpu variants. */
67 73
68 -struct sparc_opcode_arch { 74 +typedef struct sparc_opcode_arch
  75 +{
69 const char *name; 76 const char *name;
70 /* Mask of sparc_opcode_arch_val's supported. 77 /* Mask of sparc_opcode_arch_val's supported.
71 EG: For v7 this would be 78 EG: For v7 this would be
72 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 79 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
73 These are short's because sparc_opcode.architecture is. */ 80 These are short's because sparc_opcode.architecture is. */
74 short supported; 81 short supported;
75 -}; 82 +} sparc_opcode_arch;
76 83
77 static const struct sparc_opcode_arch sparc_opcode_archs[]; 84 static const struct sparc_opcode_arch sparc_opcode_archs[];
78 85
@@ -82,44 +89,43 @@ static const struct sparc_opcode_arch sparc_opcode_archs[]; @@ -82,44 +89,43 @@ static const struct sparc_opcode_arch sparc_opcode_archs[];
82 /* Non-zero if ARCH1 conflicts with ARCH2. 89 /* Non-zero if ARCH1 conflicts with ARCH2.
83 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 90 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
84 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 91 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
85 -(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \  
86 - != SPARC_OPCODE_SUPPORTED (ARCH1)) \  
87 - && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 92 + (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
  93 + != SPARC_OPCODE_SUPPORTED (ARCH1)) \
  94 + && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
88 != SPARC_OPCODE_SUPPORTED (ARCH2))) 95 != SPARC_OPCODE_SUPPORTED (ARCH2)))
89 96
90 /* Structure of an opcode table entry. */ 97 /* Structure of an opcode table entry. */
91 98
92 -struct sparc_opcode { 99 +typedef struct sparc_opcode
  100 +{
93 const char *name; 101 const char *name;
94 - unsigned long match; /* Bits that must be set. */  
95 - unsigned long lose; /* Bits that must not be set. */ 102 + unsigned long match; /* Bits that must be set. */
  103 + unsigned long lose; /* Bits that must not be set. */
96 const char *args; 104 const char *args;
97 - /* This was called "delayed" in versions before the flags. */ 105 + /* This was called "delayed" in versions before the flags. */
98 char flags; 106 char flags;
99 short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 107 short architecture; /* Bitmask of sparc_opcode_arch_val's. */
100 -};  
101 -  
102 -#define F_DELAYED 1 /* Delayed branch */  
103 -#define F_ALIAS 2 /* Alias for a "real" instruction */  
104 -#define F_UNBR 4 /* Unconditional branch */  
105 -#define F_CONDBR 8 /* Conditional branch */  
106 -#define F_JSR 16 /* Subroutine call */  
107 -#define F_FLOAT 32 /* Floating point instruction (not a branch) */  
108 -#define F_FBR 64 /* Floating point branch */ 108 +} sparc_opcode;
  109 +
  110 +#define F_DELAYED 1 /* Delayed branch. */
  111 +#define F_ALIAS 2 /* Alias for a "real" instruction. */
  112 +#define F_UNBR 4 /* Unconditional branch. */
  113 +#define F_CONDBR 8 /* Conditional branch. */
  114 +#define F_JSR 16 /* Subroutine call. */
  115 +#define F_FLOAT 32 /* Floating point instruction (not a branch). */
  116 +#define F_FBR 64 /* Floating point branch. */
109 /* FIXME: Add F_ANACHRONISTIC flag for v9. */ 117 /* FIXME: Add F_ANACHRONISTIC flag for v9. */
110 118
111 -/*  
112 -  
113 -All sparc opcodes are 32 bits, except for the `set' instruction (really a  
114 -macro), which is 64 bits. It is handled as a special case. 119 +/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
  120 + macro), which is 64 bits. It is handled as a special case.
115 121
116 -The match component is a mask saying which bits must match a particular  
117 -opcode in order for an instruction to be an instance of that opcode. 122 + The match component is a mask saying which bits must match a particular
  123 + opcode in order for an instruction to be an instance of that opcode.
118 124
119 -The args component is a string containing one character for each operand of the  
120 -instruction. 125 + The args component is a string containing one character for each operand of the
  126 + instruction.
121 127
122 -Kinds of operands: 128 + Kinds of operands:
123 # Number used by optimizer. It is ignored. 129 # Number used by optimizer. It is ignored.
124 1 rs1 register. 130 1 rs1 register.
125 2 rs2 register. 131 2 rs2 register.
@@ -187,49 +193,78 @@ Kinds of operands: @@ -187,49 +193,78 @@ Kinds of operands:
187 _ Ancillary state register in rd (v9a) 193 _ Ancillary state register in rd (v9a)
188 / Ancillary state register in rs1 (v9a) 194 / Ancillary state register in rs1 (v9a)
189 195
190 -The following chars are unused: (note: ,[] are used as punctuation)  
191 -[45]  
192 -  
193 -*/  
194 -  
195 -#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */  
196 -#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */  
197 -#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */  
198 -#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */  
199 -#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */  
200 -#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */  
201 -#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */  
202 -#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */  
203 -#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */  
204 -#define F1(x) (OP(x))  
205 -#define DISP30(x) ((x)&0x3fffffff)  
206 -#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */  
207 -#define RS2(x) ((x)&0x1f) /* rs2 field */  
208 -#define SIMM13(x) ((x)&0x1fff) /* simm13 field */  
209 -#define RD(x) (((x)&0x1f) << 25) /* destination register field */  
210 -#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */  
211 -#define ASI_RS2(x) (SIMM13(x))  
212 -#define MEMBAR(x) ((x)&0x7f)  
213 -#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */  
214 -  
215 -#define ANNUL (1<<29)  
216 -#define BPRED (1<<19) /* v9 */  
217 -#define IMMED F3I(1)  
218 -#define RD_G0 RD(~0)  
219 -#define RS1_G0 RS1(~0)  
220 -#define RS2_G0 RS2(~0) 196 + The following chars are unused: (note: ,[] are used as punctuation)
  197 + [45]. */
  198 +
  199 +#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
  200 +#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
  201 +#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
  202 +#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
  203 +#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
  204 +#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
  205 +#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
  206 +#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
  207 +#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
  208 +#define F1(x) (OP (x))
  209 +#define DISP30(x) ((x) & 0x3fffffff)
  210 +#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
  211 +#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
  212 +#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
  213 +#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
  214 +#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
  215 +#define ASI_RS2(x) (SIMM13 (x))
  216 +#define MEMBAR(x) ((x) & 0x7f)
  217 +#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
  218 +
  219 +#define ANNUL (1 << 29)
  220 +#define BPRED (1 << 19) /* V9. */
  221 +#define IMMED F3I (1)
  222 +#define RD_G0 RD (~0)
  223 +#define RS1_G0 RS1 (~0)
  224 +#define RS2_G0 RS2 (~0)
221 225
222 static const struct sparc_opcode sparc_opcodes[]; 226 static const struct sparc_opcode sparc_opcodes[];
223 static const int sparc_num_opcodes; 227 static const int sparc_num_opcodes;
224 228
225 -static const char *sparc_decode_asi_v8 PARAMS ((int));  
226 -static const char *sparc_decode_asi_v9 PARAMS ((int));  
227 -static const char *sparc_decode_membar PARAMS ((int));  
228 -static const char *sparc_decode_prefetch PARAMS ((int));  
229 -static const char *sparc_decode_sparclet_cpreg PARAMS ((int)); 229 +static const char *sparc_decode_asi_v8 (int);
  230 +static const char *sparc_decode_asi_v9 (int);
  231 +static const char *sparc_decode_membar (int);
  232 +static const char *sparc_decode_prefetch (int);
  233 +static const char *sparc_decode_sparclet_cpreg (int);
  234 +
  235 +/* Local Variables:
  236 + fill-column: 131
  237 + comment-column: 0
  238 + End: */
230 239
231 /* opcodes/sparc-opc.c */ 240 /* opcodes/sparc-opc.c */
232 241
  242 +/* Table of opcodes for the sparc.
  243 + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
  244 + 2000, 2002, 2004, 2005
  245 + Free Software Foundation, Inc.
  246 +
  247 + This file is part of the BFD library.
  248 +
  249 + BFD is free software; you can redistribute it and/or modify it under
  250 + the terms of the GNU General Public License as published by the Free
  251 + Software Foundation; either version 2, or (at your option) any later
  252 + version.
  253 +
  254 + BFD is distributed in the hope that it will be useful, but WITHOUT ANY
  255 + WARRANTY; without even the implied warranty of MERCHANTABILITY or
  256 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  257 + for more details.
  258 +
  259 + You should have received a copy of the GNU General Public License
  260 + along with this software; see the file COPYING. If not, write to
  261 + the Free Software Foundation, 51 Franklin Street - Fifth Floor,
  262 + Boston, MA 02110-1301, USA. */
  263 +
  264 +/* FIXME-someday: perhaps the ,a's and such should be embedded in the
  265 + instruction's name rather than the args. This would make gas faster, pinsn
  266 + slower, but would mess up some macros a bit. xoxorich. */
  267 +
233 /* Some defines to make life easy. */ 268 /* Some defines to make life easy. */
234 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) 269 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
235 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) 270 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
@@ -244,7 +279,7 @@ static const char *sparc_decode_sparclet_cpreg PARAMS ((int)); @@ -244,7 +279,7 @@ static const char *sparc_decode_sparclet_cpreg PARAMS ((int));
244 279
245 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ 280 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
246 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) 281 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
247 -/* v6 insns not supported on the sparclet */ 282 +/* v6 insns not supported on the sparclet. */
248 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ 283 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
249 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) 284 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
250 #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ 285 #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
@@ -262,17 +297,18 @@ static const char *sparc_decode_sparclet_cpreg PARAMS ((int)); @@ -262,17 +297,18 @@ static const char *sparc_decode_sparclet_cpreg PARAMS ((int));
262 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B) 297 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
263 #define v9a (MASK_V9A | MASK_V9B) 298 #define v9a (MASK_V9A | MASK_V9B)
264 #define v9b (MASK_V9B) 299 #define v9b (MASK_V9B)
265 -/* v6 insns not supported by v9 */ 300 +/* v6 insns not supported by v9. */
266 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ 301 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
267 | MASK_SPARCLET | MASK_SPARCLITE) 302 | MASK_SPARCLET | MASK_SPARCLITE)
268 /* v9a instructions which would appear to be aliases to v9's impdep's 303 /* v9a instructions which would appear to be aliases to v9's impdep's
269 - otherwise */ 304 + otherwise. */
270 #define v9notv9a (MASK_V9) 305 #define v9notv9a (MASK_V9)
271 306
272 /* Table of opcode architectures. 307 /* Table of opcode architectures.
273 The order is defined in opcode/sparc.h. */ 308 The order is defined in opcode/sparc.h. */
274 309
275 -static const struct sparc_opcode_arch sparc_opcode_archs[] = { 310 +static const struct sparc_opcode_arch sparc_opcode_archs[] =
  311 +{
276 { "v6", MASK_V6 }, 312 { "v6", MASK_V6 },
277 { "v7", MASK_V6 | MASK_V7 }, 313 { "v7", MASK_V6 | MASK_V7 },
278 { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, 314 { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
@@ -288,69 +324,67 @@ static const struct sparc_opcode_arch sparc_opcode_archs[] = { @@ -288,69 +324,67 @@ static const struct sparc_opcode_arch sparc_opcode_archs[] = {
288 }; 324 };
289 325
290 /* Branch condition field. */ 326 /* Branch condition field. */
291 -#define COND(x) (((x)&0xf)<<25) 327 +#define COND(x) (((x) & 0xf) << 25)
292 328
293 /* v9: Move (MOVcc and FMOVcc) condition field. */ 329 /* v9: Move (MOVcc and FMOVcc) condition field. */
294 -#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ 330 +#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
295 331
296 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ 332 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */
297 -#define RCOND(x) (((x)&0x7)<<10) /* v9 */  
298 -  
299 -#define CONDA (COND(0x8))  
300 -#define CONDCC (COND(0xd))  
301 -#define CONDCS (COND(0x5))  
302 -#define CONDE (COND(0x1))  
303 -#define CONDG (COND(0xa))  
304 -#define CONDGE (COND(0xb))  
305 -#define CONDGU (COND(0xc))  
306 -#define CONDL (COND(0x3))  
307 -#define CONDLE (COND(0x2))  
308 -#define CONDLEU (COND(0x4))  
309 -#define CONDN (COND(0x0))  
310 -#define CONDNE (COND(0x9))  
311 -#define CONDNEG (COND(0x6))  
312 -#define CONDPOS (COND(0xe))  
313 -#define CONDVC (COND(0xf))  
314 -#define CONDVS (COND(0x7)) 333 +#define RCOND(x) (((x) & 0x7) << 10) /* v9 */
  334 +
  335 +#define CONDA (COND (0x8))
  336 +#define CONDCC (COND (0xd))
  337 +#define CONDCS (COND (0x5))
  338 +#define CONDE (COND (0x1))
  339 +#define CONDG (COND (0xa))
  340 +#define CONDGE (COND (0xb))
  341 +#define CONDGU (COND (0xc))
  342 +#define CONDL (COND (0x3))
  343 +#define CONDLE (COND (0x2))
  344 +#define CONDLEU (COND (0x4))
  345 +#define CONDN (COND (0x0))
  346 +#define CONDNE (COND (0x9))
  347 +#define CONDNEG (COND (0x6))
  348 +#define CONDPOS (COND (0xe))
  349 +#define CONDVC (COND (0xf))
  350 +#define CONDVS (COND (0x7))
315 351
316 #define CONDNZ CONDNE 352 #define CONDNZ CONDNE
317 #define CONDZ CONDE 353 #define CONDZ CONDE
318 #define CONDGEU CONDCC 354 #define CONDGEU CONDCC
319 #define CONDLU CONDCS 355 #define CONDLU CONDCS
320 356
321 -#define FCONDA (COND(0x8))  
322 -#define FCONDE (COND(0x9))  
323 -#define FCONDG (COND(0x6))  
324 -#define FCONDGE (COND(0xb))  
325 -#define FCONDL (COND(0x4))  
326 -#define FCONDLE (COND(0xd))  
327 -#define FCONDLG (COND(0x2))  
328 -#define FCONDN (COND(0x0))  
329 -#define FCONDNE (COND(0x1))  
330 -#define FCONDO (COND(0xf))  
331 -#define FCONDU (COND(0x7))  
332 -#define FCONDUE (COND(0xa))  
333 -#define FCONDUG (COND(0x5))  
334 -#define FCONDUGE (COND(0xc))  
335 -#define FCONDUL (COND(0x3))  
336 -#define FCONDULE (COND(0xe)) 357 +#define FCONDA (COND (0x8))
  358 +#define FCONDE (COND (0x9))
  359 +#define FCONDG (COND (0x6))
  360 +#define FCONDGE (COND (0xb))
  361 +#define FCONDL (COND (0x4))
  362 +#define FCONDLE (COND (0xd))
  363 +#define FCONDLG (COND (0x2))
  364 +#define FCONDN (COND (0x0))
  365 +#define FCONDNE (COND (0x1))
  366 +#define FCONDO (COND (0xf))
  367 +#define FCONDU (COND (0x7))
  368 +#define FCONDUE (COND (0xa))
  369 +#define FCONDUG (COND (0x5))
  370 +#define FCONDUGE (COND (0xc))
  371 +#define FCONDUL (COND (0x3))
  372 +#define FCONDULE (COND (0xe))
337 373
338 #define FCONDNZ FCONDNE 374 #define FCONDNZ FCONDNE
339 #define FCONDZ FCONDE 375 #define FCONDZ FCONDE
340 376
341 -#define ICC (0) /* v9 */  
342 -#define XCC (1<<12) /* v9 */  
343 -#define FCC(x) (((x)&0x3)<<11) /* v9 */  
344 -#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ 377 +#define ICC (0) /* v9 */
  378 +#define XCC (1 << 12) /* v9 */
  379 +#define FCC(x) (((x) & 0x3) << 11) /* v9 */
  380 +#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
345 381
346 /* The order of the opcodes in the table is significant: 382 /* The order of the opcodes in the table is significant:
347 383
348 * The assembler requires that all instances of the same mnemonic must 384 * The assembler requires that all instances of the same mnemonic must
349 be consecutive. If they aren't, the assembler will bomb at runtime. 385 be consecutive. If they aren't, the assembler will bomb at runtime.
350 386
351 - * The disassembler should not care about the order of the opcodes.  
352 -  
353 -*/ 387 + * The disassembler should not care about the order of the opcodes. */
354 388
355 /* Entries for commutative arithmetic operations. */ 389 /* Entries for commutative arithmetic operations. */
356 /* ??? More entries can make use of this. */ 390 /* ??? More entries can make use of this. */
@@ -881,6 +915,10 @@ static const struct sparc_opcode sparc_opcodes[] = { @@ -881,6 +915,10 @@ static const struct sparc_opcode sparc_opcodes[] = {
881 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, 915 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
882 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, 916 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
883 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, 917 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
  918 +{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 },
  919 +{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 },
  920 +{ "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 },
  921 +{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 },
884 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, 922 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 },
885 923
886 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, 924 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
@@ -1067,6 +1105,13 @@ static const struct sparc_opcode sparc_opcodes[] = { @@ -1067,6 +1105,13 @@ static const struct sparc_opcode sparc_opcodes[] = {
1067 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ 1105 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
1068 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ 1106 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */
1069 1107
  1108 +{ "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */
  1109 +{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */
  1110 +{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */
  1111 +{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */
  1112 +{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */
  1113 +{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */
  1114 +
1070 /* ??? This group seems wrong. A three operand move? */ 1115 /* ??? This group seems wrong. A three operand move? */
1071 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ 1116 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
1072 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ 1117 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
@@ -1458,110 +1503,72 @@ cond (&quot;bz&quot;, &quot;tz&quot;, CONDZ, F_CONDBR|F_ALIAS), /* for e */ @@ -1458,110 +1503,72 @@ cond (&quot;bz&quot;, &quot;tz&quot;, CONDZ, F_CONDBR|F_ALIAS), /* for e */
1458 #define FM_DF 2 /* v9 */ 1503 #define FM_DF 2 /* v9 */
1459 #define FM_QF 3 /* v9 */ 1504 #define FM_QF 3 /* v9 */
1460 1505
1461 -#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \  
1462 -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \  
1463 -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 } 1506 +#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
  1507 +{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \
  1508 +{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 }
1464 1509
1465 -#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \  
1466 -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \  
1467 -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \  
1468 -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \  
1469 -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 } 1510 +#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
  1511 +{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \
  1512 +{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \
  1513 +{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \
  1514 +{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 }
1470 1515
1471 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ 1516 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1472 -#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \  
1473 -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \  
1474 -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \  
1475 -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \  
1476 -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \  
1477 -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \  
1478 -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 }  
1479 -  
1480 -/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0),  
1481 -/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0),  
1482 -/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0),  
1483 -/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0),  
1484 -/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0),  
1485 -/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0),  
1486 -/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0),  
1487 -/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0),  
1488 -/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0),  
1489 -/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0),  
1490 -/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0),  
1491 -/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0),  
1492 -/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0),  
1493 -/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0),  
1494 -/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0),  
1495 -/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0),  
1496 -/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0),  
1497 -/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0),  
1498 -/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS),  
1499 -/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS),  
1500 -/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS),  
1501 -/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0),  
1502 -/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0),  
1503 -/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0),  
1504 -/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0),  
1505 -/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0),  
1506 -/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0),  
1507 -/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0),  
1508 -/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0),  
1509 -/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0),  
1510 -/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0),  
1511 -/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0),  
1512 -/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0),  
1513 -/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0),  
1514 -/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0),  
1515 -/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0),  
1516 -/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS),  
1517 -/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS),  
1518 -/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS),  
1519 -/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0),  
1520 -/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0),  
1521 -/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0),  
1522 -/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0),  
1523 -/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0),  
1524 -/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0),  
1525 -/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0),  
1526 -/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0),  
1527 -/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0),  
1528 -/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS),  
1529 -/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS),  
1530 -/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS),  
1531 -/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0),  
1532 -/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0),  
1533 -/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0),  
1534 -/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0),  
1535 -/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0),  
1536 -/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0),  
1537 -/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0),  
1538 -/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0),  
1539 -/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0),  
1540 -/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0),  
1541 -/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0),  
1542 -/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0),  
1543 -/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0),  
1544 -/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0),  
1545 -/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0),  
1546 -/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0),  
1547 -/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0),  
1548 -/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0),  
1549 -/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0),  
1550 -/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0),  
1551 -/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0),  
1552 -/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0),  
1553 -/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0),  
1554 -/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0),  
1555 -/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0),  
1556 -/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0),  
1557 -/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0),  
1558 -/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0),  
1559 -/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0),  
1560 -/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0),  
1561 -/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS),  
1562 -/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS),  
1563 -/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS),  
1564 - 1517 +#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
  1518 +{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \
  1519 +{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \
  1520 +{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \
  1521 +{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \
  1522 +{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \
  1523 +{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 }
  1524 +
  1525 +#define fmovicc(suffix, cond, flags) /* v9 */ \
  1526 +fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
  1527 +fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
  1528 +fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
  1529 +
  1530 +#define fmovfcc(suffix, fcond, flags) /* v9 */ \
  1531 +fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
  1532 +fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
  1533 +fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
  1534 +
  1535 +#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
  1536 +fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
  1537 +fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
  1538 +fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
  1539 +
  1540 +/* v9 */ fmovcc ("a", CONDA, FCONDA, 0),
  1541 +/* v9 */ fmovicc ("cc", CONDCC, 0),
  1542 +/* v9 */ fmovicc ("cs", CONDCS, 0),
  1543 +/* v9 */ fmovcc ("e", CONDE, FCONDE, 0),
  1544 +/* v9 */ fmovcc ("g", CONDG, FCONDG, 0),
  1545 +/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0),
  1546 +/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
  1547 +/* v9 */ fmovicc ("gu", CONDGU, 0),
  1548 +/* v9 */ fmovcc ("l", CONDL, FCONDL, 0),
  1549 +/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0),
  1550 +/* v9 */ fmovicc ("leu", CONDLEU, 0),
  1551 +/* v9 */ fmovfcc ("lg", FCONDLG, 0),
  1552 +/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
  1553 +/* v9 */ fmovcc ("n", CONDN, FCONDN, 0),
  1554 +/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0),
  1555 +/* v9 */ fmovicc ("neg", CONDNEG, 0),
  1556 +/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS),
  1557 +/* v9 */ fmovfcc ("o", FCONDO, 0),
  1558 +/* v9 */ fmovicc ("pos", CONDPOS, 0),
  1559 +/* v9 */ fmovfcc ("u", FCONDU, 0),
  1560 +/* v9 */ fmovfcc ("ue", FCONDUE, 0),
  1561 +/* v9 */ fmovfcc ("ug", FCONDUG, 0),
  1562 +/* v9 */ fmovfcc ("uge", FCONDUGE, 0),
  1563 +/* v9 */ fmovfcc ("ul", FCONDUL, 0),
  1564 +/* v9 */ fmovfcc ("ule", FCONDULE, 0),
  1565 +/* v9 */ fmovicc ("vc", CONDVC, 0),
  1566 +/* v9 */ fmovicc ("vs", CONDVS, 0),
  1567 +/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS),
  1568 +
  1569 +#undef fmoviccx /* v9 */
  1570 +#undef fmovfccx /* v9 */
  1571 +#undef fmovccx /* v9 */
1565 #undef fmovicc /* v9 */ 1572 #undef fmovicc /* v9 */
1566 #undef fmovfcc /* v9 */ 1573 #undef fmovfcc /* v9 */
1567 #undef fmovcc /* v9 */ 1574 #undef fmovcc /* v9 */
@@ -1571,13 +1578,13 @@ cond (&quot;bz&quot;, &quot;tz&quot;, CONDZ, F_CONDBR|F_ALIAS), /* for e */ @@ -1571,13 +1578,13 @@ cond (&quot;bz&quot;, &quot;tz&quot;, CONDZ, F_CONDBR|F_ALIAS), /* for e */
1571 1578
1572 /* Coprocessor branches. */ 1579 /* Coprocessor branches. */
1573 #define CBR(opcode, mask, lose, flags, arch) \ 1580 #define CBR(opcode, mask, lose, flags, arch) \
1574 - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \  
1575 - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch } 1581 + { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \
  1582 + { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
1576 1583
1577 /* Floating point branches. */ 1584 /* Floating point branches. */
1578 #define FBR(opcode, mask, lose, flags) \ 1585 #define FBR(opcode, mask, lose, flags) \
1579 - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \  
1580 - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 } 1586 + { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \
  1587 + { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
1581 1588
1582 /* V9 extended floating point branches. */ 1589 /* V9 extended floating point branches. */
1583 #define FBRX(opcode, mask, lose, flags) /* v9 */ \ 1590 #define FBRX(opcode, mask, lose, flags) /* v9 */ \
@@ -1710,17 +1717,17 @@ CONDFC (&quot;fbule&quot;, &quot;cb013&quot;, 0xe, F_CONDBR), @@ -1710,17 +1717,17 @@ CONDFC (&quot;fbule&quot;, &quot;cb013&quot;, 0xe, F_CONDBR),
1710 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, 1717 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
1711 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, 1718 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
1712 1719
1713 -{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 },  
1714 -{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 },  
1715 -{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, 1720 +{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
  1721 +{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
  1722 +{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
1716 1723
1717 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, 1724 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
1718 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, 1725 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
1719 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, 1726 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
1720 1727
1721 -{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 },  
1722 -{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 },  
1723 -{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, 1728 +{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
  1729 +{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
  1730 +{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
1724 1731
1725 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, 1732 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
1726 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, 1733 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
@@ -2050,16 +2057,10 @@ typedef struct @@ -2050,16 +2057,10 @@ typedef struct
2050 const char *name; 2057 const char *name;
2051 } arg; 2058 } arg;
2052 2059
2053 -/* Look up NAME in TABLE. */  
2054 -  
2055 -static const char *lookup_value PARAMS ((const arg *, int));  
2056 -  
2057 /* Look up VALUE in TABLE. */ 2060 /* Look up VALUE in TABLE. */
2058 2061
2059 static const char * 2062 static const char *
2060 -lookup_value (table, value)  
2061 - const arg *table;  
2062 - int value; 2063 +lookup_value (const arg *table, int value)
2063 { 2064 {
2064 const arg *p; 2065 const arg *p;
2065 2066
@@ -2067,7 +2068,7 @@ lookup_value (table, value) @@ -2067,7 +2068,7 @@ lookup_value (table, value)
2067 if (value == p->value) 2068 if (value == p->value)
2068 return p->name; 2069 return p->name;
2069 2070
2070 - return (char *) 0; 2071 + return NULL;
2071 } 2072 }
2072 2073
2073 /* Handle ASI's. */ 2074 /* Handle ASI's. */
@@ -2191,8 +2192,7 @@ static const arg membar_table[] = @@ -2191,8 +2192,7 @@ static const arg membar_table[] =
2191 /* Return the name for membar value VALUE or NULL if not found. */ 2192 /* Return the name for membar value VALUE or NULL if not found. */
2192 2193
2193 static const char * 2194 static const char *
2194 -sparc_decode_membar (value)  
2195 - int value; 2195 +sparc_decode_membar (int value)
2196 { 2196 {
2197 return lookup_value (membar_table, value); 2197 return lookup_value (membar_table, value);
2198 } 2198 }
@@ -2213,8 +2213,7 @@ static const arg prefetch_table[] = @@ -2213,8 +2213,7 @@ static const arg prefetch_table[] =
2213 /* Return the name for prefetch value VALUE or NULL if not found. */ 2213 /* Return the name for prefetch value VALUE or NULL if not found. */
2214 2214
2215 static const char * 2215 static const char *
2216 -sparc_decode_prefetch (value)  
2217 - int value; 2216 +sparc_decode_prefetch (int value)
2218 { 2217 {
2219 return lookup_value (prefetch_table, value); 2218 return lookup_value (prefetch_table, value);
2220 } 2219 }
@@ -2236,8 +2235,7 @@ static const arg sparclet_cpreg_table[] = @@ -2236,8 +2235,7 @@ static const arg sparclet_cpreg_table[] =
2236 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */ 2235 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2237 2236
2238 static const char * 2237 static const char *
2239 -sparc_decode_sparclet_cpreg (value)  
2240 - int value; 2238 +sparc_decode_sparclet_cpreg (int value)
2241 { 2239 {
2242 return lookup_value (sparclet_cpreg_table, value); 2240 return lookup_value (sparclet_cpreg_table, value);
2243 } 2241 }
@@ -2246,6 +2244,25 @@ sparc_decode_sparclet_cpreg (value) @@ -2246,6 +2244,25 @@ sparc_decode_sparclet_cpreg (value)
2246 2244
2247 /* opcodes/sparc-dis.c */ 2245 /* opcodes/sparc-dis.c */
2248 2246
  2247 +/* Print SPARC instructions.
  2248 + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
  2249 + 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
  2250 +
  2251 + This program is free software; you can redistribute it and/or modify
  2252 + it under the terms of the GNU General Public License as published by
  2253 + the Free Software Foundation; either version 2 of the License, or
  2254 + (at your option) any later version.
  2255 +
  2256 + This program is distributed in the hope that it will be useful,
  2257 + but WITHOUT ANY WARRANTY; without even the implied warranty of
  2258 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  2259 + GNU General Public License for more details.
  2260 +
  2261 + You should have received a copy of the GNU General Public License
  2262 + along with this program; if not, write to the Free Software
  2263 + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  2264 + MA 02110-1301, USA. */
  2265 +
2249 /* Bitmask of v9 architectures. */ 2266 /* Bitmask of v9 architectures. */
2250 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ 2267 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
2251 | (1 << SPARC_OPCODE_ARCH_V9A) \ 2268 | (1 << SPARC_OPCODE_ARCH_V9A) \
@@ -2256,7 +2273,7 @@ sparc_decode_sparclet_cpreg (value) @@ -2256,7 +2273,7 @@ sparc_decode_sparclet_cpreg (value)
2256 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) 2273 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2257 2274
2258 /* The sorted opcode table. */ 2275 /* The sorted opcode table. */
2259 -static const struct sparc_opcode **sorted_opcodes; 2276 +static const sparc_opcode **sorted_opcodes;
2260 2277
2261 /* For faster lookup, after insns are sorted they are hashed. */ 2278 /* For faster lookup, after insns are sorted they are hashed. */
2262 /* ??? I think there is room for even more improvement. */ 2279 /* ??? I think there is room for even more improvement. */
@@ -2268,17 +2285,13 @@ static const struct sparc_opcode **sorted_opcodes; @@ -2268,17 +2285,13 @@ static const struct sparc_opcode **sorted_opcodes;
2268 static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; 2285 static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
2269 #define HASH_INSN(INSN) \ 2286 #define HASH_INSN(INSN) \
2270 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) 2287 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
2271 -struct opcode_hash {  
2272 - struct opcode_hash *next;  
2273 - const struct sparc_opcode *opcode;  
2274 -};  
2275 -static struct opcode_hash *opcode_hash_table[HASH_SIZE]; 2288 +typedef struct sparc_opcode_hash
  2289 +{
  2290 + struct sparc_opcode_hash *next;
  2291 + const sparc_opcode *opcode;
  2292 +} sparc_opcode_hash;
2276 2293
2277 -static void build_hash_table  
2278 - PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));  
2279 -static int is_delayed_branch PARAMS ((unsigned long));  
2280 -static int compare_opcodes PARAMS ((const void *, const void *));  
2281 -static int compute_arch_mask PARAMS ((unsigned long)); 2294 +static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
2282 2295
2283 /* Sign-extend a value which is N bits long. */ 2296 /* Sign-extend a value which is N bits long. */
2284 #define SEX(value, bits) \ 2297 #define SEX(value, bits) \
@@ -2310,11 +2323,22 @@ static const char * const v9_priv_reg_names[] = @@ -2310,11 +2323,22 @@ static const char * const v9_priv_reg_names[] =
2310 { 2323 {
2311 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", 2324 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
2312 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", 2325 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2313 - "wstate", "fq" 2326 + "wstate", "fq", "gl"
2314 /* "ver" - special cased */ 2327 /* "ver" - special cased */
2315 }; 2328 };
2316 2329
2317 /* These are ordered according to there register number in 2330 /* These are ordered according to there register number in
  2331 + rdhpr and wrhpr insns. */
  2332 +static const char * const v9_hpriv_reg_names[] =
  2333 +{
  2334 + "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
  2335 + "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
  2336 + "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
  2337 + "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
  2338 + "resv28", "resv29", "resv30", "hstick_cmpr"
  2339 +};
  2340 +
  2341 +/* These are ordered according to there register number in
2318 rd and wr insns (-16). */ 2342 rd and wr insns (-16). */
2319 static const char * const v9a_asr_reg_names[] = 2343 static const char * const v9a_asr_reg_names[] =
2320 { 2344 {
@@ -2325,21 +2349,21 @@ static const char * const v9a_asr_reg_names[] = @@ -2325,21 +2349,21 @@ static const char * const v9a_asr_reg_names[] =
2325 /* Macros used to extract instruction fields. Not all fields have 2349 /* Macros used to extract instruction fields. Not all fields have
2326 macros defined here, only those which are actually used. */ 2350 macros defined here, only those which are actually used. */
2327 2351
2328 -#define X_RD(i) (((i) >> 25) & 0x1f)  
2329 -#define X_RS1(i) (((i) >> 14) & 0x1f)  
2330 -#define X_LDST_I(i) (((i) >> 13) & 1)  
2331 -#define X_ASI(i) (((i) >> 5) & 0xff)  
2332 -#define X_RS2(i) (((i) >> 0) & 0x1f)  
2333 -#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))  
2334 -#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))  
2335 -#define X_DISP22(i) (((i) >> 0) & 0x3fffff)  
2336 -#define X_IMM22(i) X_DISP22 (i)  
2337 -#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) 2352 +#define X_RD(i) (((i) >> 25) & 0x1f)
  2353 +#define X_RS1(i) (((i) >> 14) & 0x1f)
  2354 +#define X_LDST_I(i) (((i) >> 13) & 1)
  2355 +#define X_ASI(i) (((i) >> 5) & 0xff)
  2356 +#define X_RS2(i) (((i) >> 0) & 0x1f)
  2357 +#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
  2358 +#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
  2359 +#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
  2360 +#define X_IMM22(i) X_DISP22 (i)
  2361 +#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
2338 2362
2339 /* These are for v9. */ 2363 /* These are for v9. */
2340 -#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))  
2341 -#define X_DISP19(i) (((i) >> 0) & 0x7ffff)  
2342 -#define X_MEMBAR(i) ((i) & 0x7f) 2364 +#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
  2365 +#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
  2366 +#define X_MEMBAR(i) ((i) & 0x7f)
2343 2367
2344 /* Here is the union which was used to extract instruction fields 2368 /* Here is the union which was used to extract instruction fields
2345 before the shift and mask macros were written. 2369 before the shift and mask macros were written.
@@ -2397,23 +2421,22 @@ static const char * const v9a_asr_reg_names[] = @@ -2397,23 +2421,22 @@ static const char * const v9a_asr_reg_names[] =
2397 unsigned int adisp30:30; 2421 unsigned int adisp30:30;
2398 #define disp30 call.adisp30 2422 #define disp30 call.adisp30
2399 } call; 2423 } call;
2400 - };  
2401 -  
2402 - */ 2424 + }; */
2403 2425
2404 /* Nonzero if INSN is the opcode for a delayed branch. */ 2426 /* Nonzero if INSN is the opcode for a delayed branch. */
  2427 +
2405 static int 2428 static int
2406 -is_delayed_branch (insn)  
2407 - unsigned long insn; 2429 +is_delayed_branch (unsigned long insn)
2408 { 2430 {
2409 - struct opcode_hash *op; 2431 + sparc_opcode_hash *op;
2410 2432
2411 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 2433 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2412 { 2434 {
2413 - const struct sparc_opcode *opcode = op->opcode; 2435 + const sparc_opcode *opcode = op->opcode;
  2436 +
2414 if ((opcode->match & insn) == opcode->match 2437 if ((opcode->match & insn) == opcode->match
2415 && (opcode->lose & insn) == 0) 2438 && (opcode->lose & insn) == 0)
2416 - return (opcode->flags & F_DELAYED); 2439 + return opcode->flags & F_DELAYED;
2417 } 2440 }
2418 return 0; 2441 return 0;
2419 } 2442 }
@@ -2424,6 +2447,236 @@ is_delayed_branch (insn) @@ -2424,6 +2447,236 @@ is_delayed_branch (insn)
2424 to compare_opcodes. */ 2447 to compare_opcodes. */
2425 static unsigned int current_arch_mask; 2448 static unsigned int current_arch_mask;
2426 2449
  2450 +/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
  2451 +
  2452 +static int
  2453 +compute_arch_mask (unsigned long mach)
  2454 +{
  2455 + switch (mach)
  2456 + {
  2457 + case 0 :
  2458 + case bfd_mach_sparc :
  2459 + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
  2460 + case bfd_mach_sparc_sparclet :
  2461 + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
  2462 + case bfd_mach_sparc_sparclite :
  2463 + case bfd_mach_sparc_sparclite_le :
  2464 + /* sparclites insns are recognized by default (because that's how
  2465 + they've always been treated, for better or worse). Kludge this by
  2466 + indicating generic v8 is also selected. */
  2467 + return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
  2468 + | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
  2469 + case bfd_mach_sparc_v8plus :
  2470 + case bfd_mach_sparc_v9 :
  2471 + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
  2472 + case bfd_mach_sparc_v8plusa :
  2473 + case bfd_mach_sparc_v9a :
  2474 + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
  2475 + case bfd_mach_sparc_v8plusb :
  2476 + case bfd_mach_sparc_v9b :
  2477 + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
  2478 + }
  2479 + abort ();
  2480 +}
  2481 +
  2482 +/* Compare opcodes A and B. */
  2483 +
  2484 +static int
  2485 +compare_opcodes (const void * a, const void * b)
  2486 +{
  2487 + sparc_opcode *op0 = * (sparc_opcode **) a;
  2488 + sparc_opcode *op1 = * (sparc_opcode **) b;
  2489 + unsigned long int match0 = op0->match, match1 = op1->match;
  2490 + unsigned long int lose0 = op0->lose, lose1 = op1->lose;
  2491 + register unsigned int i;
  2492 +
  2493 + /* If one (and only one) insn isn't supported by the current architecture,
  2494 + prefer the one that is. If neither are supported, but they're both for
  2495 + the same architecture, continue processing. Otherwise (both unsupported
  2496 + and for different architectures), prefer lower numbered arch's (fudged
  2497 + by comparing the bitmasks). */
  2498 + if (op0->architecture & current_arch_mask)
  2499 + {
  2500 + if (! (op1->architecture & current_arch_mask))
  2501 + return -1;
  2502 + }
  2503 + else
  2504 + {
  2505 + if (op1->architecture & current_arch_mask)
  2506 + return 1;
  2507 + else if (op0->architecture != op1->architecture)
  2508 + return op0->architecture - op1->architecture;
  2509 + }
  2510 +
  2511 + /* If a bit is set in both match and lose, there is something
  2512 + wrong with the opcode table. */
  2513 + if (match0 & lose0)
  2514 + {
  2515 + fprintf
  2516 + (stderr,
  2517 + /* xgettext:c-format */
  2518 + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
  2519 + op0->name, match0, lose0);
  2520 + op0->lose &= ~op0->match;
  2521 + lose0 = op0->lose;
  2522 + }
  2523 +
  2524 + if (match1 & lose1)
  2525 + {
  2526 + fprintf
  2527 + (stderr,
  2528 + /* xgettext:c-format */
  2529 + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
  2530 + op1->name, match1, lose1);
  2531 + op1->lose &= ~op1->match;
  2532 + lose1 = op1->lose;
  2533 + }
  2534 +
  2535 + /* Because the bits that are variable in one opcode are constant in
  2536 + another, it is important to order the opcodes in the right order. */
  2537 + for (i = 0; i < 32; ++i)
  2538 + {
  2539 + unsigned long int x = 1 << i;
  2540 + int x0 = (match0 & x) != 0;
  2541 + int x1 = (match1 & x) != 0;
  2542 +
  2543 + if (x0 != x1)
  2544 + return x1 - x0;
  2545 + }
  2546 +
  2547 + for (i = 0; i < 32; ++i)
  2548 + {
  2549 + unsigned long int x = 1 << i;
  2550 + int x0 = (lose0 & x) != 0;
  2551 + int x1 = (lose1 & x) != 0;
  2552 +
  2553 + if (x0 != x1)
  2554 + return x1 - x0;
  2555 + }
  2556 +
  2557 + /* They are functionally equal. So as long as the opcode table is
  2558 + valid, we can put whichever one first we want, on aesthetic grounds. */
  2559 +
  2560 + /* Our first aesthetic ground is that aliases defer to real insns. */
  2561 + {
  2562 + int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
  2563 +
  2564 + if (alias_diff != 0)
  2565 + /* Put the one that isn't an alias first. */
  2566 + return alias_diff;
  2567 + }
  2568 +
  2569 + /* Except for aliases, two "identical" instructions had
  2570 + better have the same opcode. This is a sanity check on the table. */
  2571 + i = strcmp (op0->name, op1->name);
  2572 + if (i)
  2573 + {
  2574 + if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
  2575 + return i;
  2576 + else
  2577 + fprintf (stderr,
  2578 + /* xgettext:c-format */
  2579 + _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
  2580 + op0->name, op1->name);
  2581 + }
  2582 +
  2583 + /* Fewer arguments are preferred. */
  2584 + {
  2585 + int length_diff = strlen (op0->args) - strlen (op1->args);
  2586 +
  2587 + if (length_diff != 0)
  2588 + /* Put the one with fewer arguments first. */
  2589 + return length_diff;
  2590 + }
  2591 +
  2592 + /* Put 1+i before i+1. */
  2593 + {
  2594 + char *p0 = (char *) strchr (op0->args, '+');
  2595 + char *p1 = (char *) strchr (op1->args, '+');
  2596 +
  2597 + if (p0 && p1)
  2598 + {
  2599 + /* There is a plus in both operands. Note that a plus
  2600 + sign cannot be the first character in args,
  2601 + so the following [-1]'s are valid. */
  2602 + if (p0[-1] == 'i' && p1[1] == 'i')
  2603 + /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
  2604 + return 1;
  2605 + if (p0[1] == 'i' && p1[-1] == 'i')
  2606 + /* op0 is 1+i and op1 is i+1, so op0 goes first. */
  2607 + return -1;
  2608 + }
  2609 + }
  2610 +
  2611 + /* Put 1,i before i,1. */
  2612 + {
  2613 + int i0 = strncmp (op0->args, "i,1", 3) == 0;
  2614 + int i1 = strncmp (op1->args, "i,1", 3) == 0;
  2615 +
  2616 + if (i0 ^ i1)
  2617 + return i0 - i1;
  2618 + }
  2619 +
  2620 + /* They are, as far as we can tell, identical.
  2621 + Since qsort may have rearranged the table partially, there is
  2622 + no way to tell which one was first in the opcode table as
  2623 + written, so just say there are equal. */
  2624 + /* ??? This is no longer true now that we sort a vector of pointers,
  2625 + not the table itself. */
  2626 + return 0;
  2627 +}
  2628 +
  2629 +/* Build a hash table from the opcode table.
  2630 + OPCODE_TABLE is a sorted list of pointers into the opcode table. */
  2631 +
  2632 +static void
  2633 +build_hash_table (const sparc_opcode **opcode_table,
  2634 + sparc_opcode_hash **hash_table,
  2635 + int num_opcodes)
  2636 +{
  2637 + int i;
  2638 + int hash_count[HASH_SIZE];
  2639 + static sparc_opcode_hash *hash_buf = NULL;
  2640 +
  2641 + /* Start at the end of the table and work backwards so that each
  2642 + chain is sorted. */
  2643 +
  2644 + memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
  2645 + memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
  2646 + if (hash_buf != NULL)
  2647 + free (hash_buf);
  2648 + hash_buf = malloc (sizeof (* hash_buf) * num_opcodes);
  2649 + for (i = num_opcodes - 1; i >= 0; --i)
  2650 + {
  2651 + int hash = HASH_INSN (opcode_table[i]->match);
  2652 + sparc_opcode_hash *h = &hash_buf[i];
  2653 +
  2654 + h->next = hash_table[hash];
  2655 + h->opcode = opcode_table[i];
  2656 + hash_table[hash] = h;
  2657 + ++hash_count[hash];
  2658 + }
  2659 +
  2660 +#if 0 /* for debugging */
  2661 + {
  2662 + int min_count = num_opcodes, max_count = 0;
  2663 + int total;
  2664 +
  2665 + for (i = 0; i < HASH_SIZE; ++i)
  2666 + {
  2667 + if (hash_count[i] < min_count)
  2668 + min_count = hash_count[i];
  2669 + if (hash_count[i] > max_count)
  2670 + max_count = hash_count[i];
  2671 + total += hash_count[i];
  2672 + }
  2673 +
  2674 + printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
  2675 + min_count, max_count, (double) total / HASH_SIZE);
  2676 + }
  2677 +#endif
  2678 +}
  2679 +
2427 /* Print one instruction from MEMADDR on INFO->STREAM. 2680 /* Print one instruction from MEMADDR on INFO->STREAM.
2428 2681
2429 We suffix the instruction with a comment that gives the absolute 2682 We suffix the instruction with a comment that gives the absolute
@@ -2433,19 +2686,17 @@ static unsigned int current_arch_mask; @@ -2433,19 +2686,17 @@ static unsigned int current_arch_mask;
2433 on that register. */ 2686 on that register. */
2434 2687
2435 int 2688 int
2436 -print_insn_sparc (memaddr, info)  
2437 - bfd_vma memaddr;  
2438 - disassemble_info *info; 2689 +print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
2439 { 2690 {
2440 FILE *stream = info->stream; 2691 FILE *stream = info->stream;
2441 bfd_byte buffer[4]; 2692 bfd_byte buffer[4];
2442 unsigned long insn; 2693 unsigned long insn;
2443 - register struct opcode_hash *op; 2694 + sparc_opcode_hash *op;
2444 /* Nonzero of opcode table has been initialized. */ 2695 /* Nonzero of opcode table has been initialized. */
2445 static int opcodes_initialized = 0; 2696 static int opcodes_initialized = 0;
2446 /* bfd mach number of last call. */ 2697 /* bfd mach number of last call. */
2447 static unsigned long current_mach = 0; 2698 static unsigned long current_mach = 0;
2448 - bfd_vma (*getword) PARAMS ((const unsigned char *)); 2699 + bfd_vma (*getword) (const unsigned char *);
2449 2700
2450 if (!opcodes_initialized 2701 if (!opcodes_initialized
2451 || info->mach != current_mach) 2702 || info->mach != current_mach)
@@ -2455,8 +2706,8 @@ print_insn_sparc (memaddr, info) @@ -2455,8 +2706,8 @@ print_insn_sparc (memaddr, info)
2455 current_arch_mask = compute_arch_mask (info->mach); 2706 current_arch_mask = compute_arch_mask (info->mach);
2456 2707
2457 if (!opcodes_initialized) 2708 if (!opcodes_initialized)
2458 - sorted_opcodes = (const struct sparc_opcode **)  
2459 - malloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); 2709 + sorted_opcodes =
  2710 + malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
2460 /* Reset the sorted table so we can resort it. */ 2711 /* Reset the sorted table so we can resort it. */
2461 for (i = 0; i < sparc_num_opcodes; ++i) 2712 for (i = 0; i < sparc_num_opcodes; ++i)
2462 sorted_opcodes[i] = &sparc_opcodes[i]; 2713 sorted_opcodes[i] = &sparc_opcodes[i];
@@ -2471,6 +2722,7 @@ print_insn_sparc (memaddr, info) @@ -2471,6 +2722,7 @@ print_insn_sparc (memaddr, info)
2471 { 2722 {
2472 int status = 2723 int status =
2473 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); 2724 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
  2725 +
2474 if (status != 0) 2726 if (status != 0)
2475 { 2727 {
2476 (*info->memory_error_func) (status, memaddr, info); 2728 (*info->memory_error_func) (status, memaddr, info);
@@ -2479,7 +2731,7 @@ print_insn_sparc (memaddr, info) @@ -2479,7 +2731,7 @@ print_insn_sparc (memaddr, info)
2479 } 2731 }
2480 2732
2481 /* On SPARClite variants such as DANlite (sparc86x), instructions 2733 /* On SPARClite variants such as DANlite (sparc86x), instructions
2482 - are always big-endian even when the machine is in little-endian mode. */ 2734 + are always big-endian even when the machine is in little-endian mode. */
2483 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) 2735 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
2484 getword = bfd_getb32; 2736 getword = bfd_getb32;
2485 else 2737 else
@@ -2487,14 +2739,14 @@ print_insn_sparc (memaddr, info) @@ -2487,14 +2739,14 @@ print_insn_sparc (memaddr, info)
2487 2739
2488 insn = getword (buffer); 2740 insn = getword (buffer);
2489 2741
2490 - info->insn_info_valid = 1; /* We do return this info */  
2491 - info->insn_type = dis_nonbranch; /* Assume non branch insn */  
2492 - info->branch_delay_insns = 0; /* Assume no delay */  
2493 - info->target = 0; /* Assume no target known */ 2742 + info->insn_info_valid = 1; /* We do return this info. */
  2743 + info->insn_type = dis_nonbranch; /* Assume non branch insn. */
  2744 + info->branch_delay_insns = 0; /* Assume no delay. */
  2745 + info->target = 0; /* Assume no target known. */
2494 2746
2495 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 2747 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2496 { 2748 {
2497 - const struct sparc_opcode *opcode = op->opcode; 2749 + const sparc_opcode *opcode = op->opcode;
2498 2750
2499 /* If the insn isn't supported by the current architecture, skip it. */ 2751 /* If the insn isn't supported by the current architecture, skip it. */
2500 if (! (opcode->architecture & current_arch_mask)) 2752 if (! (opcode->architecture & current_arch_mask))
@@ -2534,36 +2786,38 @@ print_insn_sparc (memaddr, info) @@ -2534,36 +2786,38 @@ print_insn_sparc (memaddr, info)
2534 (*info->fprintf_func) (stream, opcode->name); 2786 (*info->fprintf_func) (stream, opcode->name);
2535 2787
2536 { 2788 {
2537 - register const char *s; 2789 + const char *s;
2538 2790
2539 if (opcode->args[0] != ',') 2791 if (opcode->args[0] != ',')
2540 (*info->fprintf_func) (stream, " "); 2792 (*info->fprintf_func) (stream, " ");
  2793 +
2541 for (s = opcode->args; *s != '\0'; ++s) 2794 for (s = opcode->args; *s != '\0'; ++s)
2542 { 2795 {
2543 while (*s == ',') 2796 while (*s == ',')
2544 { 2797 {
2545 (*info->fprintf_func) (stream, ","); 2798 (*info->fprintf_func) (stream, ",");
2546 ++s; 2799 ++s;
2547 - switch (*s) {  
2548 - case 'a':  
2549 - (*info->fprintf_func) (stream, "a");  
2550 - is_annulled = 1;  
2551 - ++s;  
2552 - continue;  
2553 - case 'N':  
2554 - (*info->fprintf_func) (stream, "pn");  
2555 - ++s;  
2556 - continue;  
2557 -  
2558 - case 'T':  
2559 - (*info->fprintf_func) (stream, "pt");  
2560 - ++s;  
2561 - continue;  
2562 -  
2563 - default:  
2564 - break;  
2565 - } /* switch on arg */  
2566 - } /* while there are comma started args */ 2800 + switch (*s)
  2801 + {
  2802 + case 'a':
  2803 + (*info->fprintf_func) (stream, "a");
  2804 + is_annulled = 1;
  2805 + ++s;
  2806 + continue;
  2807 + case 'N':
  2808 + (*info->fprintf_func) (stream, "pn");
  2809 + ++s;
  2810 + continue;
  2811 +
  2812 + case 'T':
  2813 + (*info->fprintf_func) (stream, "pt");
  2814 + ++s;
  2815 + continue;
  2816 +
  2817 + default:
  2818 + break;
  2819 + }
  2820 + }
2567 2821
2568 (*info->fprintf_func) (stream, " "); 2822 (*info->fprintf_func) (stream, " ");
2569 2823
@@ -2571,8 +2825,8 @@ print_insn_sparc (memaddr, info) @@ -2571,8 +2825,8 @@ print_insn_sparc (memaddr, info)
2571 { 2825 {
2572 case '+': 2826 case '+':
2573 found_plus = 1; 2827 found_plus = 1;
  2828 + /* Fall through. */
2574 2829
2575 - /* note fall-through */  
2576 default: 2830 default:
2577 (*info->fprintf_func) (stream, "%c", *s); 2831 (*info->fprintf_func) (stream, "%c", *s);
2578 break; 2832 break;
@@ -2602,24 +2856,24 @@ print_insn_sparc (memaddr, info) @@ -2602,24 +2856,24 @@ print_insn_sparc (memaddr, info)
2602 case 'e': 2856 case 'e':
2603 freg (X_RS1 (insn)); 2857 freg (X_RS1 (insn));
2604 break; 2858 break;
2605 - case 'v': /* double/even */  
2606 - case 'V': /* quad/multiple of 4 */ 2859 + case 'v': /* Double/even. */
  2860 + case 'V': /* Quad/multiple of 4. */
2607 fregx (X_RS1 (insn)); 2861 fregx (X_RS1 (insn));
2608 break; 2862 break;
2609 2863
2610 case 'f': 2864 case 'f':
2611 freg (X_RS2 (insn)); 2865 freg (X_RS2 (insn));
2612 break; 2866 break;
2613 - case 'B': /* double/even */  
2614 - case 'R': /* quad/multiple of 4 */ 2867 + case 'B': /* Double/even. */
  2868 + case 'R': /* Quad/multiple of 4. */
2615 fregx (X_RS2 (insn)); 2869 fregx (X_RS2 (insn));
2616 break; 2870 break;
2617 2871
2618 case 'g': 2872 case 'g':
2619 freg (X_RD (insn)); 2873 freg (X_RD (insn));
2620 break; 2874 break;
2621 - case 'H': /* double/even */  
2622 - case 'J': /* quad/multiple of 4 */ 2875 + case 'H': /* Double/even. */
  2876 + case 'J': /* Quad/multiple of 4. */
2623 fregx (X_RD (insn)); 2877 fregx (X_RD (insn));
2624 break; 2878 break;
2625 #undef freg 2879 #undef freg
@@ -2645,9 +2899,9 @@ print_insn_sparc (memaddr, info) @@ -2645,9 +2899,9 @@ print_insn_sparc (memaddr, info)
2645 & ((int) X_IMM22 (insn) << 10))); 2899 & ((int) X_IMM22 (insn) << 10)));
2646 break; 2900 break;
2647 2901
2648 - case 'i': /* 13 bit immediate */  
2649 - case 'I': /* 11 bit immediate */  
2650 - case 'j': /* 10 bit immediate */ 2902 + case 'i': /* 13 bit immediate. */
  2903 + case 'I': /* 11 bit immediate. */
  2904 + case 'j': /* 10 bit immediate. */
2651 { 2905 {
2652 int imm; 2906 int imm;
2653 2907
@@ -2675,8 +2929,8 @@ print_insn_sparc (memaddr, info) @@ -2675,8 +2929,8 @@ print_insn_sparc (memaddr, info)
2675 } 2929 }
2676 break; 2930 break;
2677 2931
2678 - case 'X': /* 5 bit unsigned immediate */  
2679 - case 'Y': /* 6 bit unsigned immediate */ 2932 + case 'X': /* 5 bit unsigned immediate. */
  2933 + case 'Y': /* 6 bit unsigned immediate. */
2680 { 2934 {
2681 int imm = X_IMM (insn, *s == 'X' ? 5 : 6); 2935 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
2682 2936
@@ -2688,7 +2942,7 @@ print_insn_sparc (memaddr, info) @@ -2688,7 +2942,7 @@ print_insn_sparc (memaddr, info)
2688 break; 2942 break;
2689 2943
2690 case '3': 2944 case '3':
2691 - (info->fprintf_func) (stream, "%d", X_IMM (insn, 3)); 2945 + (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
2692 break; 2946 break;
2693 2947
2694 case 'K': 2948 case 'K':
@@ -2763,7 +3017,7 @@ print_insn_sparc (memaddr, info) @@ -2763,7 +3017,7 @@ print_insn_sparc (memaddr, info)
2763 case '?': 3017 case '?':
2764 if (X_RS1 (insn) == 31) 3018 if (X_RS1 (insn) == 31)
2765 (*info->fprintf_func) (stream, "%%ver"); 3019 (*info->fprintf_func) (stream, "%%ver");
2766 - else if ((unsigned) X_RS1 (insn) < 16) 3020 + else if ((unsigned) X_RS1 (insn) < 17)
2767 (*info->fprintf_func) (stream, "%%%s", 3021 (*info->fprintf_func) (stream, "%%%s",
2768 v9_priv_reg_names[X_RS1 (insn)]); 3022 v9_priv_reg_names[X_RS1 (insn)]);
2769 else 3023 else
@@ -2771,13 +3025,29 @@ print_insn_sparc (memaddr, info) @@ -2771,13 +3025,29 @@ print_insn_sparc (memaddr, info)
2771 break; 3025 break;
2772 3026
2773 case '!': 3027 case '!':
2774 - if ((unsigned) X_RD (insn) < 15) 3028 + if ((unsigned) X_RD (insn) < 17)
2775 (*info->fprintf_func) (stream, "%%%s", 3029 (*info->fprintf_func) (stream, "%%%s",
2776 v9_priv_reg_names[X_RD (insn)]); 3030 v9_priv_reg_names[X_RD (insn)]);
2777 else 3031 else
2778 (*info->fprintf_func) (stream, "%%reserved"); 3032 (*info->fprintf_func) (stream, "%%reserved");
2779 break; 3033 break;
2780 3034
  3035 + case '$':
  3036 + if ((unsigned) X_RS1 (insn) < 32)
  3037 + (*info->fprintf_func) (stream, "%%%s",
  3038 + v9_hpriv_reg_names[X_RS1 (insn)]);
  3039 + else
  3040 + (*info->fprintf_func) (stream, "%%reserved");
  3041 + break;
  3042 +
  3043 + case '%':
  3044 + if ((unsigned) X_RD (insn) < 32)
  3045 + (*info->fprintf_func) (stream, "%%%s",
  3046 + v9_hpriv_reg_names[X_RD (insn)]);
  3047 + else
  3048 + (*info->fprintf_func) (stream, "%%reserved");
  3049 + break;
  3050 +
2781 case '/': 3051 case '/':
2782 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) 3052 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
2783 (*info->fprintf_func) (stream, "%%reserved"); 3053 (*info->fprintf_func) (stream, "%%reserved");
@@ -2801,16 +3071,16 @@ print_insn_sparc (memaddr, info) @@ -2801,16 +3071,16 @@ print_insn_sparc (memaddr, info)
2801 if (name) 3071 if (name)
2802 (*info->fprintf_func) (stream, "%s", name); 3072 (*info->fprintf_func) (stream, "%s", name);
2803 else 3073 else
2804 - (*info->fprintf_func) (stream, "%d", X_RD (insn)); 3074 + (*info->fprintf_func) (stream, "%ld", X_RD (insn));
2805 break; 3075 break;
2806 } 3076 }
2807 3077
2808 case 'M': 3078 case 'M':
2809 - (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); 3079 + (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
2810 break; 3080 break;
2811 3081
2812 case 'm': 3082 case 'm':
2813 - (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); 3083 + (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
2814 break; 3084 break;
2815 3085
2816 case 'L': 3086 case 'L':
@@ -2842,7 +3112,7 @@ print_insn_sparc (memaddr, info) @@ -2842,7 +3112,7 @@ print_insn_sparc (memaddr, info)
2842 if (name) 3112 if (name)
2843 (*info->fprintf_func) (stream, "%s", name); 3113 (*info->fprintf_func) (stream, "%s", name);
2844 else 3114 else
2845 - (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); 3115 + (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
2846 break; 3116 break;
2847 } 3117 }
2848 3118
@@ -2875,7 +3145,7 @@ print_insn_sparc (memaddr, info) @@ -2875,7 +3145,7 @@ print_insn_sparc (memaddr, info)
2875 break; 3145 break;
2876 3146
2877 case 'x': 3147 case 'x':
2878 - (*info->fprintf_func) (stream, "%d", 3148 + (*info->fprintf_func) (stream, "%ld",
2879 ((X_LDST_I (insn) << 8) 3149 ((X_LDST_I (insn) << 8)
2880 + X_ASI (insn))); 3150 + X_ASI (insn)));
2881 break; 3151 break;
@@ -2911,26 +3181,33 @@ print_insn_sparc (memaddr, info) @@ -2911,26 +3181,33 @@ print_insn_sparc (memaddr, info)
2911 unsigned long prev_insn; 3181 unsigned long prev_insn;
2912 int errcode; 3182 int errcode;
2913 3183
2914 - errcode =  
2915 - (*info->read_memory_func) 3184 + if (memaddr >= 4)
  3185 + errcode =
  3186 + (*info->read_memory_func)
2916 (memaddr - 4, buffer, sizeof (buffer), info); 3187 (memaddr - 4, buffer, sizeof (buffer), info);
  3188 + else
  3189 + errcode = 1;
  3190 +
2917 prev_insn = getword (buffer); 3191 prev_insn = getword (buffer);
2918 3192
2919 if (errcode == 0) 3193 if (errcode == 0)
2920 { 3194 {
2921 /* If it is a delayed branch, we need to look at the 3195 /* If it is a delayed branch, we need to look at the
2922 instruction before the delayed branch. This handles 3196 instruction before the delayed branch. This handles
2923 - sequences such as 3197 + sequences such as:
2924 3198
2925 sethi %o1, %hi(_foo), %o1 3199 sethi %o1, %hi(_foo), %o1
2926 call _printf 3200 call _printf
2927 - or %o1, %lo(_foo), %o1  
2928 - */ 3201 + or %o1, %lo(_foo), %o1 */
2929 3202
2930 if (is_delayed_branch (prev_insn)) 3203 if (is_delayed_branch (prev_insn))
2931 { 3204 {
2932 - errcode = (*info->read_memory_func)  
2933 - (memaddr - 8, buffer, sizeof (buffer), info); 3205 + if (memaddr >= 8)
  3206 + errcode = (*info->read_memory_func)
  3207 + (memaddr - 8, buffer, sizeof (buffer), info);
  3208 + else
  3209 + errcode = 1;
  3210 +
2934 prev_insn = getword (buffer); 3211 prev_insn = getword (buffer);
2935 } 3212 }
2936 } 3213 }
@@ -2960,7 +3237,7 @@ print_insn_sparc (memaddr, info) @@ -2960,7 +3237,7 @@ print_insn_sparc (memaddr, info)
2960 3237
2961 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) 3238 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
2962 { 3239 {
2963 - /* FIXME -- check is_annulled flag */ 3240 + /* FIXME -- check is_annulled flag. */
2964 if (opcode->flags & F_UNBR) 3241 if (opcode->flags & F_UNBR)
2965 info->insn_type = dis_branch; 3242 info->insn_type = dis_branch;
2966 if (opcode->flags & F_CONDBR) 3243 if (opcode->flags & F_CONDBR)
@@ -2975,236 +3252,7 @@ print_insn_sparc (memaddr, info) @@ -2975,236 +3252,7 @@ print_insn_sparc (memaddr, info)
2975 } 3252 }
2976 } 3253 }
2977 3254
2978 - info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ 3255 + info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
2979 (*info->fprintf_func) (stream, _("unknown")); 3256 (*info->fprintf_func) (stream, _("unknown"));
2980 return sizeof (buffer); 3257 return sizeof (buffer);
2981 } 3258 }
2982 -  
2983 -/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */  
2984 -  
2985 -static int  
2986 -compute_arch_mask (mach)  
2987 - unsigned long mach;  
2988 -{  
2989 - switch (mach)  
2990 - {  
2991 - case 0 :  
2992 - case bfd_mach_sparc :  
2993 - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);  
2994 - case bfd_mach_sparc_sparclet :  
2995 - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);  
2996 - case bfd_mach_sparc_sparclite :  
2997 - case bfd_mach_sparc_sparclite_le :  
2998 - /* sparclites insns are recognized by default (because that's how  
2999 - they've always been treated, for better or worse). Kludge this by  
3000 - indicating generic v8 is also selected. */  
3001 - return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)  
3002 - | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));  
3003 - case bfd_mach_sparc_v8plus :  
3004 - case bfd_mach_sparc_v9 :  
3005 - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);  
3006 - case bfd_mach_sparc_v8plusa :  
3007 - case bfd_mach_sparc_v9a :  
3008 - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);  
3009 - case bfd_mach_sparc_v8plusb :  
3010 - case bfd_mach_sparc_v9b :  
3011 - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);  
3012 - }  
3013 - abort ();  
3014 -}  
3015 -  
3016 -/* Compare opcodes A and B. */  
3017 -  
3018 -static int  
3019 -compare_opcodes (const void *a, const void *b)  
3020 -{  
3021 - struct sparc_opcode *op0 = * (struct sparc_opcode **) a;  
3022 - struct sparc_opcode *op1 = * (struct sparc_opcode **) b;  
3023 - unsigned long int match0 = op0->match, match1 = op1->match;  
3024 - unsigned long int lose0 = op0->lose, lose1 = op1->lose;  
3025 - register unsigned int i;  
3026 -  
3027 - /* If one (and only one) insn isn't supported by the current architecture,  
3028 - prefer the one that is. If neither are supported, but they're both for  
3029 - the same architecture, continue processing. Otherwise (both unsupported  
3030 - and for different architectures), prefer lower numbered arch's (fudged  
3031 - by comparing the bitmasks). */  
3032 - if (op0->architecture & current_arch_mask)  
3033 - {  
3034 - if (! (op1->architecture & current_arch_mask))  
3035 - return -1;  
3036 - }  
3037 - else  
3038 - {  
3039 - if (op1->architecture & current_arch_mask)  
3040 - return 1;  
3041 - else if (op0->architecture != op1->architecture)  
3042 - return op0->architecture - op1->architecture;  
3043 - }  
3044 -  
3045 - /* If a bit is set in both match and lose, there is something  
3046 - wrong with the opcode table. */  
3047 - if (match0 & lose0)  
3048 - {  
3049 - fprintf  
3050 - (stderr,  
3051 - /* xgettext:c-format */  
3052 - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),  
3053 - op0->name, match0, lose0);  
3054 - op0->lose &= ~op0->match;  
3055 - lose0 = op0->lose;  
3056 - }  
3057 -  
3058 - if (match1 & lose1)  
3059 - {  
3060 - fprintf  
3061 - (stderr,  
3062 - /* xgettext:c-format */  
3063 - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),  
3064 - op1->name, match1, lose1);  
3065 - op1->lose &= ~op1->match;  
3066 - lose1 = op1->lose;  
3067 - }  
3068 -  
3069 - /* Because the bits that are variable in one opcode are constant in  
3070 - another, it is important to order the opcodes in the right order. */  
3071 - for (i = 0; i < 32; ++i)  
3072 - {  
3073 - unsigned long int x = 1 << i;  
3074 - int x0 = (match0 & x) != 0;  
3075 - int x1 = (match1 & x) != 0;  
3076 -  
3077 - if (x0 != x1)  
3078 - return x1 - x0;  
3079 - }  
3080 -  
3081 - for (i = 0; i < 32; ++i)  
3082 - {  
3083 - unsigned long int x = 1 << i;  
3084 - int x0 = (lose0 & x) != 0;  
3085 - int x1 = (lose1 & x) != 0;  
3086 -  
3087 - if (x0 != x1)  
3088 - return x1 - x0;  
3089 - }  
3090 -  
3091 - /* They are functionally equal. So as long as the opcode table is  
3092 - valid, we can put whichever one first we want, on aesthetic grounds. */  
3093 -  
3094 - /* Our first aesthetic ground is that aliases defer to real insns. */  
3095 - {  
3096 - int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);  
3097 - if (alias_diff != 0)  
3098 - /* Put the one that isn't an alias first. */  
3099 - return alias_diff;  
3100 - }  
3101 -  
3102 - /* Except for aliases, two "identical" instructions had  
3103 - better have the same opcode. This is a sanity check on the table. */  
3104 - i = strcmp (op0->name, op1->name);  
3105 - if (i)  
3106 - {  
3107 - if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */  
3108 - return i;  
3109 - else  
3110 - fprintf (stderr,  
3111 - /* xgettext:c-format */  
3112 - _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),  
3113 - op0->name, op1->name);  
3114 - }  
3115 -  
3116 - /* Fewer arguments are preferred. */  
3117 - {  
3118 - int length_diff = strlen (op0->args) - strlen (op1->args);  
3119 - if (length_diff != 0)  
3120 - /* Put the one with fewer arguments first. */  
3121 - return length_diff;  
3122 - }  
3123 -  
3124 - /* Put 1+i before i+1. */  
3125 - {  
3126 - char *p0 = (char *) strchr (op0->args, '+');  
3127 - char *p1 = (char *) strchr (op1->args, '+');  
3128 -  
3129 - if (p0 && p1)  
3130 - {  
3131 - /* There is a plus in both operands. Note that a plus  
3132 - sign cannot be the first character in args,  
3133 - so the following [-1]'s are valid. */  
3134 - if (p0[-1] == 'i' && p1[1] == 'i')  
3135 - /* op0 is i+1 and op1 is 1+i, so op1 goes first. */  
3136 - return 1;  
3137 - if (p0[1] == 'i' && p1[-1] == 'i')  
3138 - /* op0 is 1+i and op1 is i+1, so op0 goes first. */  
3139 - return -1;  
3140 - }  
3141 - }  
3142 -  
3143 - /* Put 1,i before i,1. */  
3144 - {  
3145 - int i0 = strncmp (op0->args, "i,1", 3) == 0;  
3146 - int i1 = strncmp (op1->args, "i,1", 3) == 0;  
3147 -  
3148 - if (i0 ^ i1)  
3149 - return i0 - i1;  
3150 - }  
3151 -  
3152 - /* They are, as far as we can tell, identical.  
3153 - Since qsort may have rearranged the table partially, there is  
3154 - no way to tell which one was first in the opcode table as  
3155 - written, so just say there are equal. */  
3156 - /* ??? This is no longer true now that we sort a vector of pointers,  
3157 - not the table itself. */  
3158 - return 0;  
3159 -}  
3160 -  
3161 -/* Build a hash table from the opcode table.  
3162 - OPCODE_TABLE is a sorted list of pointers into the opcode table. */  
3163 -  
3164 -static void  
3165 -build_hash_table (opcode_table, hash_table, num_opcodes)  
3166 - const struct sparc_opcode **opcode_table;  
3167 - struct opcode_hash **hash_table;  
3168 - int num_opcodes;  
3169 -{  
3170 - register int i;  
3171 - int hash_count[HASH_SIZE];  
3172 - static struct opcode_hash *hash_buf = NULL;  
3173 -  
3174 - /* Start at the end of the table and work backwards so that each  
3175 - chain is sorted. */  
3176 -  
3177 - memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));  
3178 - memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));  
3179 - if (hash_buf != NULL)  
3180 - free (hash_buf);  
3181 - hash_buf = (struct opcode_hash *) malloc (sizeof (struct opcode_hash) * num_opcodes);  
3182 - for (i = num_opcodes - 1; i >= 0; --i)  
3183 - {  
3184 - register int hash = HASH_INSN (opcode_table[i]->match);  
3185 - register struct opcode_hash *h = &hash_buf[i];  
3186 - h->next = hash_table[hash];  
3187 - h->opcode = opcode_table[i];  
3188 - hash_table[hash] = h;  
3189 - ++hash_count[hash];  
3190 - }  
3191 -  
3192 -#if 0 /* for debugging */  
3193 - {  
3194 - int min_count = num_opcodes, max_count = 0;  
3195 - int total;  
3196 -  
3197 - for (i = 0; i < HASH_SIZE; ++i)  
3198 - {  
3199 - if (hash_count[i] < min_count)  
3200 - min_count = hash_count[i];  
3201 - if (hash_count[i] > max_count)  
3202 - max_count = hash_count[i];  
3203 - total += hash_count[i];  
3204 - }  
3205 -  
3206 - printf ("Opcode hash table stats: min %d, max %d, ave %f\n",  
3207 - min_count, max_count, (double) total / HASH_SIZE);  
3208 - }  
3209 -#endif  
3210 -}