Commit 44cd42ee4082813cc4b45117bbb6156920957e47
1 parent
86831435
CRIS: Add support for the pseudo randomized set that the mmu provides with TLB r…
…efill faults. This makes linux guests use the four way TLB set associativty. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4425 c046a42c-6fe2-441c-8c8c-71466251a162
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41 additions
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13 deletions
target-cris/cpu.h
... | ... | @@ -153,6 +153,11 @@ typedef struct CPUCRISState { |
153 | 153 | */ |
154 | 154 | uint32_t sregs[4][16]; |
155 | 155 | |
156 | + /* Linear feedback shift reg in the mmu. Used to provide pseudo | |
157 | + randomness for the 'hint' the mmu gives to sw for chosing valid | |
158 | + sets on TLB refills. */ | |
159 | + uint32_t mmu_rand_lfsr; | |
160 | + | |
156 | 161 | /* |
157 | 162 | * We just store the stores to the tlbset here for later evaluation |
158 | 163 | * when the hw needs access to them. | ... | ... |
target-cris/mmu.c
... | ... | @@ -32,6 +32,24 @@ |
32 | 32 | |
33 | 33 | #define D(x) |
34 | 34 | |
35 | +void cris_mmu_init(CPUState *env) | |
36 | +{ | |
37 | + env->mmu_rand_lfsr = 0xcccc; | |
38 | +} | |
39 | + | |
40 | +#define SR_POLYNOM 0x8805 | |
41 | +static inline unsigned int compute_polynom(unsigned int sr) | |
42 | +{ | |
43 | + unsigned int i; | |
44 | + unsigned int f; | |
45 | + | |
46 | + f = 0; | |
47 | + for (i = 0; i < 16; i++) | |
48 | + f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); | |
49 | + | |
50 | + return f; | |
51 | +} | |
52 | + | |
35 | 53 | static inline int cris_mmu_enabled(uint32_t rw_gc_cfg) |
36 | 54 | { |
37 | 55 | return (rw_gc_cfg & 12) != 0; |
... | ... | @@ -152,11 +170,14 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res, |
152 | 170 | hi = env->tlbsets[mmu][set][idx].hi; |
153 | 171 | |
154 | 172 | tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
173 | + tlb_pid = EXTRACT_FIELD(hi, 0, 7); | |
155 | 174 | tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
175 | + tlb_g = EXTRACT_FIELD(lo, 4, 4); | |
156 | 176 | |
157 | 177 | D(printf("TLB[%d][%d] v=%x vpage=%x -> pfn=%x lo=%x hi=%x\n", |
158 | 178 | i, idx, tlb_vpn, vpage, tlb_pfn, lo, hi)); |
159 | - if (tlb_vpn == vpage) { | |
179 | + if ((tlb_g || (tlb_pid == (env->pregs[PR_PID] & 0xff))) | |
180 | + && tlb_vpn == vpage) { | |
160 | 181 | match = 1; |
161 | 182 | break; |
162 | 183 | } |
... | ... | @@ -169,9 +190,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res, |
169 | 190 | cfg_x = EXTRACT_FIELD(r_cfg, 17, 17); |
170 | 191 | cfg_v = EXTRACT_FIELD(r_cfg, 16, 16); |
171 | 192 | |
172 | - tlb_pid = EXTRACT_FIELD(hi, 0, 7); | |
173 | 193 | tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
174 | - tlb_g = EXTRACT_FIELD(lo, 4, 4); | |
175 | 194 | tlb_v = EXTRACT_FIELD(lo, 3, 3); |
176 | 195 | tlb_k = EXTRACT_FIELD(lo, 2, 2); |
177 | 196 | tlb_w = EXTRACT_FIELD(lo, 1, 1); |
... | ... | @@ -187,13 +206,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res, |
187 | 206 | set_exception_vector(0x0a, d_mmu_access); |
188 | 207 | set_exception_vector(0x0b, d_mmu_write); |
189 | 208 | */ |
190 | - if (!tlb_g | |
191 | - && tlb_pid != (env->pregs[PR_PID] & 0xff)) { | |
192 | - D(printf ("tlb: wrong pid %x %x pc=%x\n", | |
193 | - tlb_pid, env->pregs[PR_PID], env->pc)); | |
194 | - match = 0; | |
195 | - res->bf_vec = vect_base; | |
196 | - } else if (cfg_k && tlb_k && usermode) { | |
209 | + if (cfg_k && tlb_k && usermode) { | |
197 | 210 | D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", |
198 | 211 | vaddr, lo, env->pc)); |
199 | 212 | match = 0; |
... | ... | @@ -229,17 +242,27 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res, |
229 | 242 | |
230 | 243 | env->sregs[SFR_RW_MM_TLB_HI] = hi; |
231 | 244 | env->sregs[SFR_RW_MM_TLB_LO] = lo; |
245 | + } else { | |
246 | + /* If refill, provide a randomized set. */ | |
247 | + set = env->mmu_rand_lfsr & 3; | |
232 | 248 | } |
233 | 249 | |
234 | 250 | if (!match) { |
235 | - /* miss. */ | |
251 | + unsigned int f; | |
252 | + | |
253 | + /* Update lfsr at every fault. */ | |
254 | + f = compute_polynom(env->mmu_rand_lfsr); | |
255 | + env->mmu_rand_lfsr >>= 1; | |
256 | + env->mmu_rand_lfsr |= (f << 15); | |
257 | + env->mmu_rand_lfsr &= 0xffff; | |
258 | + | |
259 | + /* Compute index. */ | |
236 | 260 | idx = vpage & 15; |
237 | - set = 0; | |
238 | 261 | |
239 | 262 | /* Update RW_MM_TLB_SEL. */ |
240 | 263 | env->sregs[SFR_RW_MM_TLB_SEL] = 0; |
241 | 264 | set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); |
242 | - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 5); | |
265 | + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); | |
243 | 266 | |
244 | 267 | /* Update RW_MM_CAUSE. */ |
245 | 268 | set_field(&r_cause, rwcause, 8, 2); | ... | ... |