Commit 43d4145a986d97197eb56fd0858175823ad9d96e
1 parent
295defa5
bfd.h dependancy removed
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@75 c046a42c-6fe2-441c-8c8c-71466251a162
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dis-asm.h
| ... | ... | @@ -11,7 +11,152 @@ |
| 11 | 11 | |
| 12 | 12 | #include <stdio.h> |
| 13 | 13 | #include <string.h> |
| 14 | -#include "bfd.h" | |
| 14 | +#include <inttypes.h> | |
| 15 | + | |
| 16 | +#define PARAMS(x) x | |
| 17 | +typedef void *PTR; | |
| 18 | +typedef uint64_t bfd_vma; | |
| 19 | +typedef uint8_t bfd_byte; | |
| 20 | + | |
| 21 | +enum bfd_flavour { | |
| 22 | + bfd_target_unknown_flavour, | |
| 23 | + bfd_target_aout_flavour, | |
| 24 | + bfd_target_coff_flavour, | |
| 25 | + bfd_target_ecoff_flavour, | |
| 26 | + bfd_target_elf_flavour, | |
| 27 | + bfd_target_ieee_flavour, | |
| 28 | + bfd_target_nlm_flavour, | |
| 29 | + bfd_target_oasys_flavour, | |
| 30 | + bfd_target_tekhex_flavour, | |
| 31 | + bfd_target_srec_flavour, | |
| 32 | + bfd_target_ihex_flavour, | |
| 33 | + bfd_target_som_flavour, | |
| 34 | + bfd_target_os9k_flavour, | |
| 35 | + bfd_target_versados_flavour, | |
| 36 | + bfd_target_msdos_flavour, | |
| 37 | + bfd_target_evax_flavour | |
| 38 | +}; | |
| 39 | + | |
| 40 | +enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN }; | |
| 41 | + | |
| 42 | +enum bfd_architecture | |
| 43 | +{ | |
| 44 | + bfd_arch_unknown, /* File arch not known */ | |
| 45 | + bfd_arch_obscure, /* Arch known, not one of these */ | |
| 46 | + bfd_arch_m68k, /* Motorola 68xxx */ | |
| 47 | +#define bfd_mach_m68000 1 | |
| 48 | +#define bfd_mach_m68008 2 | |
| 49 | +#define bfd_mach_m68010 3 | |
| 50 | +#define bfd_mach_m68020 4 | |
| 51 | +#define bfd_mach_m68030 5 | |
| 52 | +#define bfd_mach_m68040 6 | |
| 53 | +#define bfd_mach_m68060 7 | |
| 54 | + bfd_arch_vax, /* DEC Vax */ | |
| 55 | + bfd_arch_i960, /* Intel 960 */ | |
| 56 | + /* The order of the following is important. | |
| 57 | + lower number indicates a machine type that | |
| 58 | + only accepts a subset of the instructions | |
| 59 | + available to machines with higher numbers. | |
| 60 | + The exception is the "ca", which is | |
| 61 | + incompatible with all other machines except | |
| 62 | + "core". */ | |
| 63 | + | |
| 64 | +#define bfd_mach_i960_core 1 | |
| 65 | +#define bfd_mach_i960_ka_sa 2 | |
| 66 | +#define bfd_mach_i960_kb_sb 3 | |
| 67 | +#define bfd_mach_i960_mc 4 | |
| 68 | +#define bfd_mach_i960_xa 5 | |
| 69 | +#define bfd_mach_i960_ca 6 | |
| 70 | +#define bfd_mach_i960_jx 7 | |
| 71 | +#define bfd_mach_i960_hx 8 | |
| 72 | + | |
| 73 | + bfd_arch_a29k, /* AMD 29000 */ | |
| 74 | + bfd_arch_sparc, /* SPARC */ | |
| 75 | +#define bfd_mach_sparc 1 | |
| 76 | + /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */ | |
| 77 | +#define bfd_mach_sparc_sparclet 2 | |
| 78 | +#define bfd_mach_sparc_sparclite 3 | |
| 79 | +#define bfd_mach_sparc_v8plus 4 | |
| 80 | +#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns */ | |
| 81 | +#define bfd_mach_sparc_v9 6 | |
| 82 | +#define bfd_mach_sparc_v9a 7 /* with ultrasparc add'ns */ | |
| 83 | + /* Nonzero if MACH has the v9 instruction set. */ | |
| 84 | +#define bfd_mach_sparc_v9_p(mach) \ | |
| 85 | + ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9a) | |
| 86 | + bfd_arch_mips, /* MIPS Rxxxx */ | |
| 87 | +#define bfd_mach_mips3000 3000 | |
| 88 | +#define bfd_mach_mips3900 3900 | |
| 89 | +#define bfd_mach_mips4000 4000 | |
| 90 | +#define bfd_mach_mips4010 4010 | |
| 91 | +#define bfd_mach_mips4100 4100 | |
| 92 | +#define bfd_mach_mips4300 4300 | |
| 93 | +#define bfd_mach_mips4400 4400 | |
| 94 | +#define bfd_mach_mips4600 4600 | |
| 95 | +#define bfd_mach_mips4650 4650 | |
| 96 | +#define bfd_mach_mips5000 5000 | |
| 97 | +#define bfd_mach_mips6000 6000 | |
| 98 | +#define bfd_mach_mips8000 8000 | |
| 99 | +#define bfd_mach_mips10000 10000 | |
| 100 | +#define bfd_mach_mips16 16 | |
| 101 | + bfd_arch_i386, /* Intel 386 */ | |
| 102 | +#define bfd_mach_i386_i386 0 | |
| 103 | +#define bfd_mach_i386_i8086 1 | |
| 104 | + bfd_arch_we32k, /* AT&T WE32xxx */ | |
| 105 | + bfd_arch_tahoe, /* CCI/Harris Tahoe */ | |
| 106 | + bfd_arch_i860, /* Intel 860 */ | |
| 107 | + bfd_arch_romp, /* IBM ROMP PC/RT */ | |
| 108 | + bfd_arch_alliant, /* Alliant */ | |
| 109 | + bfd_arch_convex, /* Convex */ | |
| 110 | + bfd_arch_m88k, /* Motorola 88xxx */ | |
| 111 | + bfd_arch_pyramid, /* Pyramid Technology */ | |
| 112 | + bfd_arch_h8300, /* Hitachi H8/300 */ | |
| 113 | +#define bfd_mach_h8300 1 | |
| 114 | +#define bfd_mach_h8300h 2 | |
| 115 | +#define bfd_mach_h8300s 3 | |
| 116 | + bfd_arch_powerpc, /* PowerPC */ | |
| 117 | + bfd_arch_rs6000, /* IBM RS/6000 */ | |
| 118 | + bfd_arch_hppa, /* HP PA RISC */ | |
| 119 | + bfd_arch_d10v, /* Mitsubishi D10V */ | |
| 120 | + bfd_arch_z8k, /* Zilog Z8000 */ | |
| 121 | +#define bfd_mach_z8001 1 | |
| 122 | +#define bfd_mach_z8002 2 | |
| 123 | + bfd_arch_h8500, /* Hitachi H8/500 */ | |
| 124 | + bfd_arch_sh, /* Hitachi SH */ | |
| 125 | +#define bfd_mach_sh 0 | |
| 126 | +#define bfd_mach_sh3 0x30 | |
| 127 | +#define bfd_mach_sh3e 0x3e | |
| 128 | +#define bfd_mach_sh4 0x40 | |
| 129 | + bfd_arch_alpha, /* Dec Alpha */ | |
| 130 | + bfd_arch_arm, /* Advanced Risc Machines ARM */ | |
| 131 | +#define bfd_mach_arm_2 1 | |
| 132 | +#define bfd_mach_arm_2a 2 | |
| 133 | +#define bfd_mach_arm_3 3 | |
| 134 | +#define bfd_mach_arm_3M 4 | |
| 135 | +#define bfd_mach_arm_4 5 | |
| 136 | +#define bfd_mach_arm_4T 6 | |
| 137 | + bfd_arch_ns32k, /* National Semiconductors ns32000 */ | |
| 138 | + bfd_arch_w65, /* WDC 65816 */ | |
| 139 | + bfd_arch_tic30, /* Texas Instruments TMS320C30 */ | |
| 140 | + bfd_arch_v850, /* NEC V850 */ | |
| 141 | +#define bfd_mach_v850 0 | |
| 142 | + bfd_arch_arc, /* Argonaut RISC Core */ | |
| 143 | +#define bfd_mach_arc_base 0 | |
| 144 | + bfd_arch_m32r, /* Mitsubishi M32R/D */ | |
| 145 | +#define bfd_mach_m32r 0 /* backwards compatibility */ | |
| 146 | + bfd_arch_mn10200, /* Matsushita MN10200 */ | |
| 147 | + bfd_arch_mn10300, /* Matsushita MN10300 */ | |
| 148 | + bfd_arch_last | |
| 149 | + }; | |
| 150 | + | |
| 151 | +typedef struct symbol_cache_entry | |
| 152 | +{ | |
| 153 | + const char *name; | |
| 154 | + union | |
| 155 | + { | |
| 156 | + PTR p; | |
| 157 | + bfd_vma i; | |
| 158 | + } udata; | |
| 159 | +} asymbol; | |
| 15 | 160 | |
| 16 | 161 | typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...)); |
| 17 | 162 | |
| ... | ... | @@ -176,8 +321,10 @@ extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*)); |
| 176 | 321 | extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); |
| 177 | 322 | extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); |
| 178 | 323 | |
| 324 | +#if 0 | |
| 179 | 325 | /* Fetch the disassembler for a given BFD, if that support is available. */ |
| 180 | 326 | extern disassembler_ftype disassembler PARAMS ((bfd *)); |
| 327 | +#endif | |
| 181 | 328 | |
| 182 | 329 | |
| 183 | 330 | /* This block of definitions is for particular callers who read instructions | ... | ... |