Commit 42f1ced228c9b616cfa2b69846025271618e4ef5
1 parent
eae6bcbf
Don't set IRQs on device reset and loadvm/savevm
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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5 changed files
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0 additions
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12 deletions
hw/esp.c
| @@ -401,8 +401,6 @@ static void esp_reset(void *opaque) | @@ -401,8 +401,6 @@ static void esp_reset(void *opaque) | ||
| 401 | { | 401 | { |
| 402 | ESPState *s = opaque; | 402 | ESPState *s = opaque; |
| 403 | 403 | ||
| 404 | - esp_lower_irq(s); | ||
| 405 | - | ||
| 406 | memset(s->rregs, 0, ESP_REGS); | 404 | memset(s->rregs, 0, ESP_REGS); |
| 407 | memset(s->wregs, 0, ESP_REGS); | 405 | memset(s->wregs, 0, ESP_REGS); |
| 408 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a | 406 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a |
hw/iommu.c
| @@ -362,7 +362,6 @@ static void iommu_reset(void *opaque) | @@ -362,7 +362,6 @@ static void iommu_reset(void *opaque) | ||
| 362 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; | 362 | s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
| 363 | s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; | 363 | s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
| 364 | s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; | 364 | s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
| 365 | - qemu_irq_lower(s->irq); | ||
| 366 | } | 365 | } |
| 367 | 366 | ||
| 368 | void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) | 367 | void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
hw/sbi.c
| @@ -47,10 +47,6 @@ typedef struct SBIState { | @@ -47,10 +47,6 @@ typedef struct SBIState { | ||
| 47 | 47 | ||
| 48 | #define SBI_SIZE (SBI_NREGS * 4) | 48 | #define SBI_SIZE (SBI_NREGS * 4) |
| 49 | 49 | ||
| 50 | -static void sbi_check_interrupts(void *opaque) | ||
| 51 | -{ | ||
| 52 | -} | ||
| 53 | - | ||
| 54 | static void sbi_set_irq(void *opaque, int irq, int level) | 50 | static void sbi_set_irq(void *opaque, int irq, int level) |
| 55 | { | 51 | { |
| 56 | } | 52 | } |
| @@ -122,7 +118,6 @@ static int sbi_load(QEMUFile *f, void *opaque, int version_id) | @@ -122,7 +118,6 @@ static int sbi_load(QEMUFile *f, void *opaque, int version_id) | ||
| 122 | for (i = 0; i < MAX_CPUS; i++) { | 118 | for (i = 0; i < MAX_CPUS; i++) { |
| 123 | qemu_get_be32s(f, &s->intreg_pending[i]); | 119 | qemu_get_be32s(f, &s->intreg_pending[i]); |
| 124 | } | 120 | } |
| 125 | - sbi_check_interrupts(s); | ||
| 126 | 121 | ||
| 127 | return 0; | 122 | return 0; |
| 128 | } | 123 | } |
| @@ -135,7 +130,6 @@ static void sbi_reset(void *opaque) | @@ -135,7 +130,6 @@ static void sbi_reset(void *opaque) | ||
| 135 | for (i = 0; i < MAX_CPUS; i++) { | 130 | for (i = 0; i < MAX_CPUS; i++) { |
| 136 | s->intreg_pending[i] = 0; | 131 | s->intreg_pending[i] = 0; |
| 137 | } | 132 | } |
| 138 | - sbi_check_interrupts(s); | ||
| 139 | } | 133 | } |
| 140 | 134 | ||
| 141 | void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, | 135 | void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, |
hw/slavio_timer.c
| @@ -359,7 +359,6 @@ static void slavio_timer_reset(void *opaque) | @@ -359,7 +359,6 @@ static void slavio_timer_reset(void *opaque) | ||
| 359 | ptimer_run(s->timer, 0); | 359 | ptimer_run(s->timer, 0); |
| 360 | } | 360 | } |
| 361 | s->running = 1; | 361 | s->running = 1; |
| 362 | - qemu_irq_lower(s->irq); | ||
| 363 | } | 362 | } |
| 364 | 363 | ||
| 365 | static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, | 364 | static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr, |
hw/sun4c_intctl.c
| @@ -183,7 +183,6 @@ static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id) | @@ -183,7 +183,6 @@ static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id) | ||
| 183 | 183 | ||
| 184 | qemu_get_8s(f, &s->reg); | 184 | qemu_get_8s(f, &s->reg); |
| 185 | qemu_get_8s(f, &s->pending); | 185 | qemu_get_8s(f, &s->pending); |
| 186 | - sun4c_check_interrupts(s); | ||
| 187 | 186 | ||
| 188 | return 0; | 187 | return 0; |
| 189 | } | 188 | } |
| @@ -194,7 +193,6 @@ static void sun4c_intctl_reset(void *opaque) | @@ -194,7 +193,6 @@ static void sun4c_intctl_reset(void *opaque) | ||
| 194 | 193 | ||
| 195 | s->reg = 1; | 194 | s->reg = 1; |
| 196 | s->pending = 0; | 195 | s->pending = 0; |
| 197 | - sun4c_check_interrupts(s); | ||
| 198 | } | 196 | } |
| 199 | 197 | ||
| 200 | void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, | 198 | void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq, |