gwj / at91sam9263 · Commits

Commit 41db460791c2d6a5d59a39614f2f63a5fca6d73e

Authored by aurel32
1 parent d45f89f4

target-mips: optimize write to env->hflags 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6941 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 7 additions and 14 deletions
target-mips/translate.c
  View file @41db460
@@ -429,8 +429,8 @@ enum { @@ -429,8 +429,8 @@ enum {
429 static TCGv_ptr cpu_env; 429 static TCGv_ptr cpu_env;
430 static TCGv cpu_gpr[32], cpu_PC; 430 static TCGv cpu_gpr[32], cpu_PC;
431 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC]; 431 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
432 -static TCGv cpu_dspctrl, btarget;  
433 -static TCGv bcond; 432 +static TCGv cpu_dspctrl, btarget, bcond;
  433 +static TCGv_i32 hflags;
434 static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32]; 434 static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32];
435 static TCGv_i32 fpu_fcr0, fpu_fcr31; 435 static TCGv_i32 fpu_fcr0, fpu_fcr31;
436 436
@@ -758,11 +758,7 @@ static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) @@ -758,11 +758,7 @@ static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
758 ctx->saved_pc = ctx->pc; 758 ctx->saved_pc = ctx->pc;
759 } 759 }
760 if (ctx->hflags != ctx->saved_hflags) { 760 if (ctx->hflags != ctx->saved_hflags) {
761 - TCGv_i32 r_tmp = tcg_temp_new_i32();  
762 -  
763 - tcg_gen_movi_i32(r_tmp, ctx->hflags);  
764 - tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));  
765 - tcg_temp_free_i32(r_tmp); 761 + tcg_gen_movi_i32(hflags, ctx->hflags);
766 ctx->saved_hflags = ctx->hflags; 762 ctx->saved_hflags = ctx->hflags;
767 switch (ctx->hflags & MIPS_HFLAG_BMASK) { 763 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
768 case MIPS_HFLAG_BR: 764 case MIPS_HFLAG_BR:
@@ -7555,13 +7551,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -7555,13 +7551,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7555 7551
7556 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4); 7552 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
7557 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 7553 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
7558 - {  
7559 - TCGv_i32 r_tmp = tcg_temp_new_i32();  
7560 -  
7561 - tcg_gen_movi_i32(r_tmp, ctx->hflags & ~MIPS_HFLAG_BMASK);  
7562 - tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));  
7563 - tcg_temp_free_i32(r_tmp);  
7564 - } 7554 + tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
7565 gen_goto_tb(ctx, 1, ctx->pc + 4); 7555 gen_goto_tb(ctx, 1, ctx->pc + 4);
7566 gen_set_label(l1); 7556 gen_set_label(l1);
7567 } 7557 }
@@ -8413,6 +8403,9 @@ static void mips_tcg_init(void) @@ -8413,6 +8403,9 @@ static void mips_tcg_init(void)
8413 offsetof(CPUState, bcond), "bcond"); 8403 offsetof(CPUState, bcond), "bcond");
8414 btarget = tcg_global_mem_new(TCG_AREG0, 8404 btarget = tcg_global_mem_new(TCG_AREG0,
8415 offsetof(CPUState, btarget), "btarget"); 8405 offsetof(CPUState, btarget), "btarget");
  8406 + hflags = tcg_global_mem_new_i32(TCG_AREG0,
  8407 + offsetof(CPUState, hflags), "hflags");
  8408 +
8416 for (i = 0; i < 32; i++) 8409 for (i = 0; i < 32; i++)
8417 fpu_fpr32[i] = tcg_global_mem_new_i32(TCG_AREG0, 8410 fpu_fpr32[i] = tcg_global_mem_new_i32(TCG_AREG0,
8418 offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]), 8411 offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]),