gwj / at91sam9263 · Commits

Commit 41d728522b6f269b636fe5e2bc91b399a23e5a4c

Authored by Blue Swirl
1 parent 67526b20

Optimize operations with immediate parameters

Inline Side-by-side
Showing 1 changed file with 200 additions and 52 deletions
target-sparc/translate.c
  View file @41d7285
... ... @@ -446,17 +446,43 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2)
446 446 gen_set_label(l1);
447 447 }
448 448  
  449 +static inline void gen_op_add_cc2(TCGv dst)
  450 +{
  451 + gen_cc_clear_icc();
  452 + gen_cc_NZ_icc(cpu_cc_dst);
  453 + gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
  454 + gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
  455 +#ifdef TARGET_SPARC64
  456 + gen_cc_clear_xcc();
  457 + gen_cc_NZ_xcc(cpu_cc_dst);
  458 + gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
  459 + gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
  460 +#endif
  461 + tcg_gen_mov_tl(dst, cpu_cc_dst);
  462 +}
  463 +
  464 +static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)
  465 +{
  466 + tcg_gen_mov_tl(cpu_cc_src, src1);
  467 + tcg_gen_movi_tl(cpu_cc_src2, src2);
  468 + tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);
  469 + gen_op_add_cc2(dst);
  470 +}
  471 +
449 472 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
450 473 {
451 474 tcg_gen_mov_tl(cpu_cc_src, src1);
452 475 tcg_gen_mov_tl(cpu_cc_src2, src2);
453 476 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
454   - gen_cc_clear_icc();
  477 + gen_op_add_cc2(dst);
  478 +}
  479 +
  480 +static inline void gen_op_addx_cc2(TCGv dst)
  481 +{
455 482 gen_cc_NZ_icc(cpu_cc_dst);
456 483 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
457 484 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
458 485 #ifdef TARGET_SPARC64
459   - gen_cc_clear_xcc();
460 486 gen_cc_NZ_xcc(cpu_cc_dst);
461 487 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
462 488 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
... ... @@ -464,10 +490,10 @@ static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
464 490 tcg_gen_mov_tl(dst, cpu_cc_dst);
465 491 }
466 492  
467   -static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
  493 +static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2)
468 494 {
469 495 tcg_gen_mov_tl(cpu_cc_src, src1);
470   - tcg_gen_mov_tl(cpu_cc_src2, src2);
  496 + tcg_gen_movi_tl(cpu_cc_src2, src2);
471 497 gen_mov_reg_C(cpu_tmp0, cpu_psr);
472 498 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
473 499 gen_cc_clear_icc();
... ... @@ -476,16 +502,24 @@ static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
476 502 gen_cc_clear_xcc();
477 503 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
478 504 #endif
479   - tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
480   - gen_cc_NZ_icc(cpu_cc_dst);
  505 + tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2);
  506 + gen_op_addx_cc2(dst);
  507 +}
  508 +
  509 +static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
  510 +{
  511 + tcg_gen_mov_tl(cpu_cc_src, src1);
  512 + tcg_gen_mov_tl(cpu_cc_src2, src2);
  513 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  514 + tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
  515 + gen_cc_clear_icc();
481 516 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
482   - gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
483 517 #ifdef TARGET_SPARC64
484   - gen_cc_NZ_xcc(cpu_cc_dst);
  518 + gen_cc_clear_xcc();
485 519 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
486   - gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
487 520 #endif
488   - tcg_gen_mov_tl(dst, cpu_cc_dst);
  521 + tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
  522 + gen_op_addx_cc2(dst);
489 523 }
490 524  
491 525 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
... ... @@ -616,11 +650,8 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
616 650 tcg_temp_free(r_temp);
617 651 }
618 652  
619   -static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
  653 +static inline void gen_op_sub_cc2(TCGv dst)
620 654 {
621   - tcg_gen_mov_tl(cpu_cc_src, src1);
622   - tcg_gen_mov_tl(cpu_cc_src2, src2);
623   - tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
624 655 gen_cc_clear_icc();
625 656 gen_cc_NZ_icc(cpu_cc_dst);
626 657 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
... ... @@ -634,10 +665,39 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
634 665 tcg_gen_mov_tl(dst, cpu_cc_dst);
635 666 }
636 667  
637   -static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
  668 +static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2)
  669 +{
  670 + tcg_gen_mov_tl(cpu_cc_src, src1);
  671 + tcg_gen_movi_tl(cpu_cc_src2, src2);
  672 + tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
  673 + gen_op_sub_cc2(dst);
  674 +}
  675 +
  676 +static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
638 677 {
639 678 tcg_gen_mov_tl(cpu_cc_src, src1);
640 679 tcg_gen_mov_tl(cpu_cc_src2, src2);
  680 + tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
  681 + gen_op_sub_cc2(dst);
  682 +}
  683 +
  684 +static inline void gen_op_subx_cc2(TCGv dst)
  685 +{
  686 + gen_cc_NZ_icc(cpu_cc_dst);
  687 + gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
  688 + gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
  689 +#ifdef TARGET_SPARC64
  690 + gen_cc_NZ_xcc(cpu_cc_dst);
  691 + gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
  692 + gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
  693 +#endif
  694 + tcg_gen_mov_tl(dst, cpu_cc_dst);
  695 +}
  696 +
  697 +static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2)
  698 +{
  699 + tcg_gen_mov_tl(cpu_cc_src, src1);
  700 + tcg_gen_movi_tl(cpu_cc_src2, src2);
641 701 gen_mov_reg_C(cpu_tmp0, cpu_psr);
642 702 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
643 703 gen_cc_clear_icc();
... ... @@ -646,16 +706,24 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
646 706 gen_cc_clear_xcc();
647 707 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
648 708 #endif
649   - tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
650   - gen_cc_NZ_icc(cpu_cc_dst);
  709 + tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2);
  710 + gen_op_subx_cc2(dst);
  711 +}
  712 +
  713 +static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
  714 +{
  715 + tcg_gen_mov_tl(cpu_cc_src, src1);
  716 + tcg_gen_mov_tl(cpu_cc_src2, src2);
  717 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  718 + tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
  719 + gen_cc_clear_icc();
651 720 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
652   - gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
653 721 #ifdef TARGET_SPARC64
654   - gen_cc_NZ_xcc(cpu_cc_dst);
  722 + gen_cc_clear_xcc();
655 723 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
656   - gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
657 724 #endif
658   - tcg_gen_mov_tl(dst, cpu_cc_dst);
  725 + tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
  726 + gen_op_subx_cc2(dst);
659 727 }
660 728  
661 729 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
... ... @@ -3064,65 +3132,132 @@ static void disas_sparc_insn(DisasContext * dc)
3064 3132 gen_movl_TN_reg(rd, cpu_dst);
3065 3133 #endif
3066 3134 } else if (xop < 0x36) {
3067   - cpu_src1 = get_src1(insn, cpu_src1);
3068   - cpu_src2 = get_src2(insn, cpu_src2);
3069 3135 if (xop < 0x20) {
  3136 + cpu_src1 = get_src1(insn, cpu_src1);
  3137 + cpu_src2 = get_src2(insn, cpu_src2);
3070 3138 switch (xop & ~0x10) {
3071 3139 case 0x0:
3072   - if (xop & 0x10)
3073   - gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3074   - else
3075   - tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
  3140 + if (IS_IMM) {
  3141 + simm = GET_FIELDs(insn, 19, 31);
  3142 + if (xop & 0x10) {
  3143 + gen_op_addi_cc(cpu_dst, cpu_src1, simm);
  3144 + } else {
  3145 + tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
  3146 + }
  3147 + } else {
  3148 + if (xop & 0x10) {
  3149 + gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
  3150 + } else {
  3151 + tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
  3152 + }
  3153 + }
3076 3154 break;
3077 3155 case 0x1:
3078   - tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3079   - if (xop & 0x10)
  3156 + if (IS_IMM) {
  3157 + simm = GET_FIELDs(insn, 19, 31);
  3158 + tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
  3159 + } else {
  3160 + tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
  3161 + }
  3162 + if (xop & 0x10) {
3080 3163 gen_op_logic_cc(cpu_dst);
  3164 + }
3081 3165 break;
3082 3166 case 0x2:
3083   - tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
  3167 + if (IS_IMM) {
  3168 + simm = GET_FIELDs(insn, 19, 31);
  3169 + tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
  3170 + } else {
  3171 + tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
  3172 + }
3084 3173 if (xop & 0x10)
3085 3174 gen_op_logic_cc(cpu_dst);
3086 3175 break;
3087 3176 case 0x3:
3088   - tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
  3177 + if (IS_IMM) {
  3178 + simm = GET_FIELDs(insn, 19, 31);
  3179 + tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
  3180 + } else {
  3181 + tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
  3182 + }
3089 3183 if (xop & 0x10)
3090 3184 gen_op_logic_cc(cpu_dst);
3091 3185 break;
3092 3186 case 0x4:
3093   - if (xop & 0x10)
3094   - gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3095   - else
3096   - tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
  3187 + if (IS_IMM) {
  3188 + simm = GET_FIELDs(insn, 19, 31);
  3189 + if (xop & 0x10) {
  3190 + gen_op_subi_cc(cpu_dst, cpu_src1, simm);
  3191 + } else {
  3192 + tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
  3193 + }
  3194 + } else {
  3195 + if (xop & 0x10) {
  3196 + gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
  3197 + } else {
  3198 + tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
  3199 + }
  3200 + }
3097 3201 break;
3098 3202 case 0x5:
3099   - tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
  3203 + if (IS_IMM) {
  3204 + simm = GET_FIELDs(insn, 19, 31);
  3205 + tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
  3206 + } else {
  3207 + tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
  3208 + }
3100 3209 if (xop & 0x10)
3101 3210 gen_op_logic_cc(cpu_dst);
3102 3211 break;
3103 3212 case 0x6:
3104   - tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
  3213 + if (IS_IMM) {
  3214 + simm = GET_FIELDs(insn, 19, 31);
  3215 + tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
  3216 + } else {
  3217 + tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
  3218 + }
3105 3219 if (xop & 0x10)
3106 3220 gen_op_logic_cc(cpu_dst);
3107 3221 break;
3108 3222 case 0x7:
3109   - tcg_gen_not_tl(cpu_tmp0, cpu_src2);
3110   - tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3223 + if (IS_IMM) {
  3224 + simm = GET_FIELDs(insn, 19, 31);
  3225 + tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
  3226 + } else {
  3227 + tcg_gen_not_tl(cpu_tmp0, cpu_src2);
  3228 + tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3229 + }
3111 3230 if (xop & 0x10)
3112 3231 gen_op_logic_cc(cpu_dst);
3113 3232 break;
3114 3233 case 0x8:
3115   - if (xop & 0x10)
3116   - gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3117   - else {
3118   - gen_mov_reg_C(cpu_tmp0, cpu_psr);
3119   - tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3120   - tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3234 + if (IS_IMM) {
  3235 + simm = GET_FIELDs(insn, 19, 31);
  3236 + if (xop & 0x10)
  3237 + gen_op_addxi_cc(cpu_dst, cpu_src1, simm);
  3238 + else {
  3239 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  3240 + tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
  3241 + tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3242 + }
  3243 + } else {
  3244 + if (xop & 0x10)
  3245 + gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
  3246 + else {
  3247 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  3248 + tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
  3249 + tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3250 + }
3121 3251 }
3122 3252 break;
3123 3253 #ifdef TARGET_SPARC64
3124 3254 case 0x9: /* V9 mulx */
3125   - tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
  3255 + if (IS_IMM) {
  3256 + simm = GET_FIELDs(insn, 19, 31);
  3257 + tcg_gen_muli_i64(cpu_dst, cpu_src1, simm);
  3258 + } else {
  3259 + tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
  3260 + }
3126 3261 break;
3127 3262 #endif
3128 3263 case 0xa:
... ... @@ -3138,12 +3273,23 @@ static void disas_sparc_insn(DisasContext * dc)
3138 3273 gen_op_logic_cc(cpu_dst);
3139 3274 break;
3140 3275 case 0xc:
3141   - if (xop & 0x10)
3142   - gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3143   - else {
3144   - gen_mov_reg_C(cpu_tmp0, cpu_psr);
3145   - tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3146   - tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3276 + if (IS_IMM) {
  3277 + simm = GET_FIELDs(insn, 19, 31);
  3278 + if (xop & 0x10) {
  3279 + gen_op_subxi_cc(cpu_dst, cpu_src1, simm);
  3280 + } else {
  3281 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  3282 + tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
  3283 + tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3284 + }
  3285 + } else {
  3286 + if (xop & 0x10) {
  3287 + gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
  3288 + } else {
  3289 + gen_mov_reg_C(cpu_tmp0, cpu_psr);
  3290 + tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
  3291 + tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
  3292 + }
3147 3293 }
3148 3294 break;
3149 3295 #ifdef TARGET_SPARC64
... ... @@ -3171,6 +3317,8 @@ static void disas_sparc_insn(DisasContext * dc)
3171 3317 }
3172 3318 gen_movl_TN_reg(rd, cpu_dst);
3173 3319 } else {
  3320 + cpu_src1 = get_src1(insn, cpu_src1);
  3321 + cpu_src2 = get_src2(insn, cpu_src2);
3174 3322 switch (xop) {
3175 3323 case 0x20: /* taddcc */
3176 3324 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
... ...