Commit 417f38f066e21cf69f85d78eecbf6268c53a80bc
1 parent
2d37be61
MIPS FPU fixes (Daniel Jacobowitz).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2213 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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5 additions
and
3 deletions
target-mips/op.c
@@ -799,7 +799,7 @@ FLOAT_OP(cvtd, w) | @@ -799,7 +799,7 @@ FLOAT_OP(cvtd, w) | ||
799 | } | 799 | } |
800 | FLOAT_OP(cvts, d) | 800 | FLOAT_OP(cvts, d) |
801 | { | 801 | { |
802 | - FST2 = float64_to_float32(WT0, &env->fp_status); | 802 | + FST2 = float64_to_float32(FDT0, &env->fp_status); |
803 | DEBUG_FPU_STATE(); | 803 | DEBUG_FPU_STATE(); |
804 | RETURN(); | 804 | RETURN(); |
805 | } | 805 | } |
target-mips/translate.c
@@ -1791,7 +1791,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int | @@ -1791,7 +1791,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int | ||
1791 | break; | 1791 | break; |
1792 | case FOP(32, 17): /* cvt.s.d */ | 1792 | case FOP(32, 17): /* cvt.s.d */ |
1793 | CHECK_FR(ctx, fs | fd); | 1793 | CHECK_FR(ctx, fs | fd); |
1794 | - GEN_LOAD_FREG_FTN(WT0, fs); | 1794 | + GEN_LOAD_FREG_FTN(DT0, fs); |
1795 | gen_op_float_cvts_d(); | 1795 | gen_op_float_cvts_d(); |
1796 | GEN_STORE_FTN_FREG(fd, WT2); | 1796 | GEN_STORE_FTN_FREG(fd, WT2); |
1797 | opn = "cvt.s.d"; | 1797 | opn = "cvt.s.d"; |
@@ -1812,7 +1812,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int | @@ -1812,7 +1812,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int | ||
1812 | break; | 1812 | break; |
1813 | case FOP(36, 17): /* cvt.w.d */ | 1813 | case FOP(36, 17): /* cvt.w.d */ |
1814 | CHECK_FR(ctx, fs | fd); | 1814 | CHECK_FR(ctx, fs | fd); |
1815 | - GEN_LOAD_FREG_FTN(WT0, fs); | 1815 | + GEN_LOAD_FREG_FTN(DT0, fs); |
1816 | gen_op_float_cvtw_d(); | 1816 | gen_op_float_cvtw_d(); |
1817 | GEN_STORE_FTN_FREG(fd, WT2); | 1817 | GEN_STORE_FTN_FREG(fd, WT2); |
1818 | opn = "cvt.w.d"; | 1818 | opn = "cvt.w.d"; |
@@ -2089,6 +2089,7 @@ static void decode_opc (DisasContext *ctx) | @@ -2089,6 +2089,7 @@ static void decode_opc (DisasContext *ctx) | ||
2089 | case 0x39: /* SWC1 */ | 2089 | case 0x39: /* SWC1 */ |
2090 | case 0x3D: /* SDC1 */ | 2090 | case 0x3D: /* SDC1 */ |
2091 | #if defined(MIPS_USES_FPU) | 2091 | #if defined(MIPS_USES_FPU) |
2092 | + save_cpu_state(ctx, 1); | ||
2092 | gen_op_cp1_enabled(); | 2093 | gen_op_cp1_enabled(); |
2093 | gen_flt_ldst(ctx, op, rt, rs, imm); | 2094 | gen_flt_ldst(ctx, op, rt, rs, imm); |
2094 | #else | 2095 | #else |
@@ -2098,6 +2099,7 @@ static void decode_opc (DisasContext *ctx) | @@ -2098,6 +2099,7 @@ static void decode_opc (DisasContext *ctx) | ||
2098 | 2099 | ||
2099 | case 0x11: /* CP1 opcode */ | 2100 | case 0x11: /* CP1 opcode */ |
2100 | #if defined(MIPS_USES_FPU) | 2101 | #if defined(MIPS_USES_FPU) |
2102 | + save_cpu_state(ctx, 1); | ||
2101 | gen_op_cp1_enabled(); | 2103 | gen_op_cp1_enabled(); |
2102 | op1 = ((ctx->opcode >> 21) & 0x1F); | 2104 | op1 = ((ctx->opcode >> 21) & 0x1F); |
2103 | switch (op1) { | 2105 | switch (op1) { |