gwj / at91sam9263 · Commits

Commit 41107bcbc2ab9e2d53637976fc6f048ffa983dbb

Authored by Edgar E. Iglesias
1 parent 562183de

ETRAX: DMA fixes for 64bit hosts. 

Mainly to remove warnings.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Inline Side-by-side
Showing 1 changed file with 25 additions and 26 deletions
hw/etraxfs_dma.c
  View file @41107bc
... ... @@ -51,7 +51,7 @@
51 51  
52 52 // ------------------------------------------------------------ dma_descr_group
53 53 typedef struct dma_descr_group {
54   - struct dma_descr_group *next;
  54 + uint32_t next;
55 55 unsigned eol : 1;
56 56 unsigned tol : 1;
57 57 unsigned bol : 1;
... ... @@ -71,7 +71,7 @@ typedef struct dma_descr_group {
71 71  
72 72 // ---------------------------------------------------------- dma_descr_context
73 73 typedef struct dma_descr_context {
74   - struct dma_descr_context *next;
  74 + uint32_t next;
75 75 unsigned eol : 1;
76 76 unsigned : 3;
77 77 unsigned intr : 1;
... ... @@ -85,14 +85,14 @@ typedef struct dma_descr_context {
85 85 unsigned md2;
86 86 unsigned md3;
87 87 unsigned md4;
88   - struct dma_descr_data *saved_data;
89   - char *saved_data_buf;
  88 + uint32_t saved_data;
  89 + uint32_t saved_data_buf;
90 90 } dma_descr_context;
91 91  
92 92 // ------------------------------------------------------------- dma_descr_data
93 93 typedef struct dma_descr_data {
94   - struct dma_descr_data *next;
95   - char *buf;
  94 + uint32_t next;
  95 + uint32_t buf;
96 96 unsigned eol : 1;
97 97 unsigned : 2;
98 98 unsigned out_eop : 1;
... ... @@ -103,7 +103,7 @@ typedef struct dma_descr_data {
103 103 unsigned in_eop : 1;
104 104 unsigned : 4;
105 105 unsigned md : 16;
106   - char *after;
  106 + uint32_t after;
107 107 } dma_descr_data;
108 108  
109 109 /* Constants */
... ... @@ -233,18 +233,18 @@ static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
233 233 static void dump_c(int ch, struct dma_descr_context *c)
234 234 {
235 235 printf("%s ch=%d\n", __func__, ch);
236   - printf("next=%p\n", c->next);
237   - printf("saved_data=%p\n", c->saved_data);
238   - printf("saved_data_buf=%p\n", c->saved_data_buf);
  236 + printf("next=%x\n", c->next);
  237 + printf("saved_data=%x\n", c->saved_data);
  238 + printf("saved_data_buf=%x\n", c->saved_data_buf);
239 239 printf("eol=%x\n", (uint32_t) c->eol);
240 240 }
241 241  
242 242 static void dump_d(int ch, struct dma_descr_data *d)
243 243 {
244 244 printf("%s ch=%d\n", __func__, ch);
245   - printf("next=%p\n", d->next);
246   - printf("buf=%p\n", d->buf);
247   - printf("after=%p\n", d->after);
  245 + printf("next=%x\n", d->next);
  246 + printf("buf=%x\n", d->buf);
  247 + printf("after=%x\n", d->after);
248 248 printf("intr=%x\n", (uint32_t) d->intr);
249 249 printf("out_eop=%x\n", (uint32_t) d->out_eop);
250 250 printf("in_eop=%x\n", (uint32_t) d->in_eop);
... ... @@ -274,7 +274,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
274 274 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
275 275  
276 276 /* Load and decode. FIXME: handle endianness. */
277   - D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
  277 + D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
278 278 cpu_physical_memory_read (addr,
279 279 (void *) &ctrl->channels[c].current_d,
280 280 sizeof ctrl->channels[c].current_d);
... ... @@ -288,7 +288,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
288 288 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
289 289  
290 290 /* Encode and store. FIXME: handle endianness. */
291   - D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
  291 + D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
292 292 D(dump_d(c, &ctrl->channels[c].current_d));
293 293 cpu_physical_memory_write (addr,
294 294 (void *) &ctrl->channels[c].current_c,
... ... @@ -300,7 +300,7 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
300 300 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
301 301  
302 302 /* Encode and store. FIXME: handle endianness. */
303   - D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
  303 + D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
304 304 cpu_physical_memory_write (addr,
305 305 (void *) &ctrl->channels[c].current_d,
306 306 sizeof ctrl->channels[c].current_d);
... ... @@ -347,7 +347,7 @@ static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
347 347 /* If the current descriptor cleared the eol flag and we had already
348 348 reached eol state, do the continue. */
349 349 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
350   - D(printf("continue %d ok %p\n", c,
  350 + D(printf("continue %d ok %x\n", c,
351 351 ctrl->channels[c].current_d.next));
352 352 ctrl->channels[c].regs[RW_SAVED_DATA] =
353 353 (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
... ... @@ -406,11 +406,10 @@ static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
406 406 return 0;
407 407  
408 408 do {
409   - D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
  409 + D(printf("ch=%d buf=%x after=%x\n",
410 410 c,
411 411 (uint32_t)ctrl->channels[c].current_d.buf,
412   - (uint32_t)ctrl->channels[c].current_d.after,
413   - saved_data_buf));
  412 + (uint32_t)ctrl->channels[c].current_d.after));
414 413  
415 414 channel_load_d(ctrl, c);
416 415 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
... ... @@ -507,8 +506,7 @@ static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
507 506 D(printf("in dscr end len=%d\n",
508 507 ctrl->channels[c].current_d.after
509 508 - ctrl->channels[c].current_d.buf));
510   - ctrl->channels[c].current_d.after =
511   - (void *)(unsigned long) saved_data_buf;
  509 + ctrl->channels[c].current_d.after = saved_data_buf;
512 510  
513 511 /* Done. Step to next. */
514 512 if (ctrl->channels[c].current_d.intr) {
... ... @@ -562,7 +560,7 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
562 560  
563 561 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
564 562 {
565   - hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
  563 + hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
566 564 return 0;
567 565 }
568 566  
... ... @@ -587,7 +585,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
587 585  
588 586 default:
589 587 r = ctrl->channels[c].regs[addr];
590   - D(printf ("%s c=%d addr=%x\n",
  588 + D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n",
591 589 __func__, c, addr));
592 590 break;
593 591 }
... ... @@ -597,7 +595,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
597 595 static void
598 596 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
599 597 {
600   - hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
  598 + hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
601 599 }
602 600  
603 601 static void
... ... @@ -666,7 +664,8 @@ dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
666 664 break;
667 665  
668 666 default:
669   - D(printf ("%s c=%d %x %x\n", __func__, c, addr));
  667 + D(printf ("%s c=%d " TARGET_FMT_plx "\n",
  668 + __func__, c, addr));
670 669 break;
671 670 }
672 671 }
... ...