gwj / at91sam9263 · Commits

Commit 4017190e2d75882a0e9dbc40f403e584e0ab46c4

Authored by blueswir1
1 parent 0bb3602c

Add SuperSPARC MMU breakpoint registers (Robert Reif) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6125 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 45 additions and 1 deletions
target-sparc/cpu.h
  View file @4017190
@@ -301,6 +301,7 @@ typedef struct CPUSPARCState { @@ -301,6 +301,7 @@ typedef struct CPUSPARCState {
301 uint32_t mmuregs[32]; 301 uint32_t mmuregs[32];
302 uint64_t mxccdata[4]; 302 uint64_t mxccdata[4];
303 uint64_t mxccregs[8]; 303 uint64_t mxccregs[8];
  304 + uint64_t mmubpregs[4];
304 uint64_t prom_addr; 305 uint64_t prom_addr;
305 #endif 306 #endif
306 /* temporary float registers */ 307 /* temporary float registers */
target-sparc/op_helper.c
  View file @4017190
@@ -953,6 +953,28 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) @@ -953,6 +953,28 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
953 case 0x39: /* data cache diagnostic register */ 953 case 0x39: /* data cache diagnostic register */
954 ret = 0; 954 ret = 0;
955 break; 955 break;
  956 + case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
  957 + {
  958 + int reg = (addr >> 8) & 3;
  959 +
  960 + switch(reg) {
  961 + case 0: /* Breakpoint Value (Addr) */
  962 + ret = env->mmubpregs[reg];
  963 + break;
  964 + case 1: /* Breakpoint Mask */
  965 + ret = env->mmubpregs[reg];
  966 + break;
  967 + case 2: /* Breakpoint Control */
  968 + ret = env->mmubpregs[reg];
  969 + break;
  970 + case 3: /* Breakpoint Status */
  971 + ret = env->mmubpregs[reg];
  972 + env->mmubpregs[reg] = 0ULL;
  973 + break;
  974 + }
  975 + DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
  976 + }
  977 + break;
956 case 8: /* User code access, XXX */ 978 case 8: /* User code access, XXX */
957 default: 979 default:
958 do_unassigned_access(addr, 0, 0, asi, size); 980 do_unassigned_access(addr, 0, 0, asi, size);
@@ -1283,9 +1305,30 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) @@ -1283,9 +1305,30 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1283 // descriptor diagnostic 1305 // descriptor diagnostic
1284 case 0x36: /* I-cache flash clear */ 1306 case 0x36: /* I-cache flash clear */
1285 case 0x37: /* D-cache flash clear */ 1307 case 0x37: /* D-cache flash clear */
1286 - case 0x38: /* breakpoint diagnostics */  
1287 case 0x4c: /* breakpoint action */ 1308 case 0x4c: /* breakpoint action */
1288 break; 1309 break;
  1310 + case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
  1311 + {
  1312 + int reg = (addr >> 8) & 3;
  1313 +
  1314 + switch(reg) {
  1315 + case 0: /* Breakpoint Value (Addr) */
  1316 + env->mmubpregs[reg] = (val & 0xfffffffffULL);
  1317 + break;
  1318 + case 1: /* Breakpoint Mask */
  1319 + env->mmubpregs[reg] = (val & 0xfffffffffULL);
  1320 + break;
  1321 + case 2: /* Breakpoint Control */
  1322 + env->mmubpregs[reg] = (val & 0x7fULL);
  1323 + break;
  1324 + case 3: /* Breakpoint Status */
  1325 + env->mmubpregs[reg] = (val & 0xfULL);
  1326 + break;
  1327 + }
  1328 + DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
  1329 + env->mmuregs[reg]);
  1330 + }
  1331 + break;
1289 case 8: /* User code access, XXX */ 1332 case 8: /* User code access, XXX */
1290 case 9: /* Supervisor code access, XXX */ 1333 case 9: /* Supervisor code access, XXX */
1291 default: 1334 default: