gwj / at91sam9263 · Commits

Commit 3f7cbbbdd4d45f30f1dfcb3905cee5e085f99011

Authored by aurel32
1 parent 52f163b7

target-ppc: fix PowerMAC NVRAM emulation 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6132 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 12 additions and 6 deletions
hw/mac_nvram.c
  View file @3f7cbbb
@@ -40,7 +40,7 @@ do { printf(&quot;NVR: &quot; fmt , ##args); } while (0) @@ -40,7 +40,7 @@ do { printf(&quot;NVR: &quot; fmt , ##args); } while (0)
40 struct MacIONVRAMState { 40 struct MacIONVRAMState {
41 target_phys_addr_t size; 41 target_phys_addr_t size;
42 int mem_index; 42 int mem_index;
43 - uint8_t data[0x2000]; 43 + uint8_t *data;
44 }; 44 };
45 45
46 /* Direct access to NVRAM */ 46 /* Direct access to NVRAM */
@@ -49,7 +49,7 @@ uint32_t macio_nvram_read (void *opaque, uint32_t addr) @@ -49,7 +49,7 @@ uint32_t macio_nvram_read (void *opaque, uint32_t addr)
49 MacIONVRAMState *s = opaque; 49 MacIONVRAMState *s = opaque;
50 uint32_t ret; 50 uint32_t ret;
51 51
52 - if (addr < 0x2000) 52 + if (addr < s->size)
53 ret = s->data[addr]; 53 ret = s->data[addr];
54 else 54 else
55 ret = -1; 55 ret = -1;
@@ -63,7 +63,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val) @@ -63,7 +63,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
63 MacIONVRAMState *s = opaque; 63 MacIONVRAMState *s = opaque;
64 64
65 NVR_DPRINTF("write addr %04x val %x\n", addr, val); 65 NVR_DPRINTF("write addr %04x val %x\n", addr, val);
66 - if (addr < 0x2000) 66 + if (addr < s->size)
67 s->data[addr] = val; 67 s->data[addr] = val;
68 } 68 }
69 69
@@ -73,7 +73,7 @@ static void macio_nvram_writeb (void *opaque, @@ -73,7 +73,7 @@ static void macio_nvram_writeb (void *opaque,
73 { 73 {
74 MacIONVRAMState *s = opaque; 74 MacIONVRAMState *s = opaque;
75 75
76 - addr = (addr >> 4) & 0x1fff; 76 + addr = (addr >> 4) & (s->size - 1);
77 s->data[addr] = value; 77 s->data[addr] = value;
78 NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value); 78 NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
79 } 79 }
@@ -83,7 +83,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) @@ -83,7 +83,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
83 MacIONVRAMState *s = opaque; 83 MacIONVRAMState *s = opaque;
84 uint32_t value; 84 uint32_t value;
85 85
86 - addr = (addr >> 4) & 0x1fff; 86 + addr = (addr >> 4) & (s->size - 1);
87 value = s->data[addr]; 87 value = s->data[addr];
88 NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value); 88 NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
89 89
@@ -109,7 +109,13 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size) @@ -109,7 +109,13 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
109 s = qemu_mallocz(sizeof(MacIONVRAMState)); 109 s = qemu_mallocz(sizeof(MacIONVRAMState));
110 if (!s) 110 if (!s)
111 return NULL; 111 return NULL;
  112 + s->data = qemu_mallocz(size);
  113 + if (!s->data) {
  114 + qemu_free(s);
  115 + return NULL;
  116 + }
112 s->size = size; 117 s->size = size;
  118 +
113 s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s); 119 s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
114 *mem_index = s->mem_index; 120 *mem_index = s->mem_index;
115 121
@@ -121,7 +127,7 @@ void macio_nvram_map (void *opaque, target_phys_addr_t mem_base) @@ -121,7 +127,7 @@ void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
121 MacIONVRAMState *s; 127 MacIONVRAMState *s;
122 128
123 s = opaque; 129 s = opaque;
124 - cpu_register_physical_memory(mem_base, s->size, s->mem_index); 130 + cpu_register_physical_memory(mem_base, s->size << 4, s->mem_index);
125 } 131 }
126 132
127 /* Set up a system OpenBIOS NVRAM partition */ 133 /* Set up a system OpenBIOS NVRAM partition */