gwj / at91sam9263 · Commits

Commit 3d575329a53ad3b72b07cea0d8f97ccc000df6ff

Authored by balrog
1 parent 7c23b892

Make SVM env->cr[8] a valid register (patch from TeLeMan). 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3950 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 6 additions and 2 deletions
target-i386/cpu.h
  View file @3d57532
@@ -493,7 +493,7 @@ typedef struct CPUX86State { @@ -493,7 +493,7 @@ typedef struct CPUX86State {
493 SegmentCache gdt; /* only base and limit are used */ 493 SegmentCache gdt; /* only base and limit are used */
494 SegmentCache idt; /* only base and limit are used */ 494 SegmentCache idt; /* only base and limit are used */
495 495
496 - target_ulong cr[5]; /* NOTE: cr1 is unused */ 496 + target_ulong cr[9]; /* NOTE: cr1, cr5-7 are unused */
497 uint32_t a20_mask; 497 uint32_t a20_mask;
498 498
499 /* FPU state */ 499 /* FPU state */
target-i386/helper.c
  View file @3d57532
@@ -2718,6 +2718,7 @@ void helper_movl_crN_T0(int reg) @@ -2718,6 +2718,7 @@ void helper_movl_crN_T0(int reg)
2718 break; 2718 break;
2719 case 8: 2719 case 8:
2720 cpu_set_apic_tpr(env, T0); 2720 cpu_set_apic_tpr(env, T0);
  2721 + env->cr[8] = T0;
2721 break; 2722 break;
2722 default: 2723 default:
2723 env->cr[reg] = T0; 2724 env->cr[reg] = T0;
@@ -4065,6 +4066,7 @@ void helper_vmrun(target_ulong addr) @@ -4065,6 +4066,7 @@ void helper_vmrun(target_ulong addr)
4065 int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); 4066 int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
4066 if (int_ctl & V_INTR_MASKING_MASK) { 4067 if (int_ctl & V_INTR_MASKING_MASK) {
4067 env->cr[8] = int_ctl & V_TPR_MASK; 4068 env->cr[8] = int_ctl & V_TPR_MASK;
  4069 + cpu_set_apic_tpr(env, env->cr[8]);
4068 if (env->eflags & IF_MASK) 4070 if (env->eflags & IF_MASK)
4069 env->hflags |= HF_HIF_MASK; 4071 env->hflags |= HF_HIF_MASK;
4070 } 4072 }
@@ -4376,8 +4378,10 @@ void vmexit(uint64_t exit_code, uint64_t exit_info_1) @@ -4376,8 +4378,10 @@ void vmexit(uint64_t exit_code, uint64_t exit_info_1)
4376 cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0)) | CR0_PE_MASK); 4378 cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0)) | CR0_PE_MASK);
4377 cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4))); 4379 cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4)));
4378 cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3))); 4380 cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3)));
4379 - if (int_ctl & V_INTR_MASKING_MASK) 4381 + if (int_ctl & V_INTR_MASKING_MASK) {
4380 env->cr[8] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr8)); 4382 env->cr[8] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr8));
  4383 + cpu_set_apic_tpr(env, env->cr[8]);
  4384 + }
4381 /* we need to set the efer after the crs so the hidden flags get set properly */ 4385 /* we need to set the efer after the crs so the hidden flags get set properly */
4382 #ifdef TARGET_X86_64 4386 #ifdef TARGET_X86_64
4383 env->efer = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer)); 4387 env->efer = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer));