gwj / at91sam9263 · Commits

Commit 3d3a6a0a48136117b8cd45dc9b1a88e7e3927d87

Authored by aurel32
1 parent b61f2753

PPC: convert SPE logical instructions to TCG 

(Nathan Froyd)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5494 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 70 additions and 56 deletions
target-ppc/op.c
  View file @3d3a6a0
@@ -2507,54 +2507,6 @@ void OPPROTO op_evcntlsw (void) @@ -2507,54 +2507,6 @@ void OPPROTO op_evcntlsw (void)
2507 RETURN(); 2507 RETURN();
2508 } 2508 }
2509 2509
2510 -void OPPROTO op_evand (void)  
2511 -{  
2512 - T0_64 &= T1_64;  
2513 - RETURN();  
2514 -}  
2515 -  
2516 -void OPPROTO op_evandc (void)  
2517 -{  
2518 - T0_64 &= ~T1_64;  
2519 - RETURN();  
2520 -}  
2521 -  
2522 -void OPPROTO op_evor (void)  
2523 -{  
2524 - T0_64 |= T1_64;  
2525 - RETURN();  
2526 -}  
2527 -  
2528 -void OPPROTO op_evxor (void)  
2529 -{  
2530 - T0_64 ^= T1_64;  
2531 - RETURN();  
2532 -}  
2533 -  
2534 -void OPPROTO op_eveqv (void)  
2535 -{  
2536 - T0_64 = ~(T0_64 ^ T1_64);  
2537 - RETURN();  
2538 -}  
2539 -  
2540 -void OPPROTO op_evnor (void)  
2541 -{  
2542 - T0_64 = ~(T0_64 | T1_64);  
2543 - RETURN();  
2544 -}  
2545 -  
2546 -void OPPROTO op_evorc (void)  
2547 -{  
2548 - T0_64 |= ~T1_64;  
2549 - RETURN();  
2550 -}  
2551 -  
2552 -void OPPROTO op_evnand (void)  
2553 -{  
2554 - T0_64 = ~(T0_64 & T1_64);  
2555 - RETURN();  
2556 -}  
2557 -  
2558 void OPPROTO op_evsrws (void) 2510 void OPPROTO op_evsrws (void)
2559 { 2511 {
2560 do_evsrws(); 2512 do_evsrws();
target-ppc/translate.c
  View file @3d3a6a0
@@ -5723,6 +5723,23 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -5723,6 +5723,23 @@ static always_inline void gen_##name (DisasContext *ctx) \
5723 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ 5723 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
5724 } 5724 }
5725 5725
  5726 +#define GEN_SPEOP_TCG_ARITH2(name) \
  5727 +static always_inline void gen_##name (DisasContext *ctx) \
  5728 +{ \
  5729 + if (unlikely(!ctx->spe_enabled)) { \
  5730 + GEN_EXCP_NO_AP(ctx); \
  5731 + return; \
  5732 + } \
  5733 + TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
  5734 + TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
  5735 + gen_load_gpr64(t0, rA(ctx->opcode)); \
  5736 + gen_load_gpr64(t1, rB(ctx->opcode)); \
  5737 + gen_op_##name(t0, t1); \
  5738 + gen_store_gpr64(rD(ctx->opcode), t0); \
  5739 + tcg_temp_free(t0); \
  5740 + tcg_temp_free(t1); \
  5741 +}
  5742 +
5726 #define GEN_SPEOP_ARITH1(name) \ 5743 #define GEN_SPEOP_ARITH1(name) \
5727 static always_inline void gen_##name (DisasContext *ctx) \ 5744 static always_inline void gen_##name (DisasContext *ctx) \
5728 { \ 5745 { \
@@ -5749,14 +5766,59 @@ static always_inline void gen_##name (DisasContext *ctx) \ @@ -5749,14 +5766,59 @@ static always_inline void gen_##name (DisasContext *ctx) \
5749 } 5766 }
5750 5767
5751 /* Logical */ 5768 /* Logical */
5752 -GEN_SPEOP_ARITH2(evand);  
5753 -GEN_SPEOP_ARITH2(evandc);  
5754 -GEN_SPEOP_ARITH2(evxor);  
5755 -GEN_SPEOP_ARITH2(evor);  
5756 -GEN_SPEOP_ARITH2(evnor);  
5757 -GEN_SPEOP_ARITH2(eveqv);  
5758 -GEN_SPEOP_ARITH2(evorc);  
5759 -GEN_SPEOP_ARITH2(evnand); 5769 +static always_inline void gen_op_evand (TCGv t0, TCGv t1)
  5770 +{
  5771 + tcg_gen_and_i64(t0, t0, t1);
  5772 +}
  5773 +
  5774 +static always_inline void gen_op_evandc (TCGv t0, TCGv t1)
  5775 +{
  5776 + tcg_gen_not_i64(t1, t1);
  5777 + tcg_gen_and_i64(t0, t0, t1);
  5778 +}
  5779 +
  5780 +static always_inline void gen_op_evxor (TCGv t0, TCGv t1)
  5781 +{
  5782 + tcg_gen_xor_i64(t0, t0, t1);
  5783 +}
  5784 +
  5785 +static always_inline void gen_op_evor (TCGv t0, TCGv t1)
  5786 +{
  5787 + tcg_gen_or_i64(t0, t0, t1);
  5788 +}
  5789 +
  5790 +static always_inline void gen_op_evnor (TCGv t0, TCGv t1)
  5791 +{
  5792 + tcg_gen_or_i64(t0, t0, t1);
  5793 + tcg_gen_not_i64(t0, t0);
  5794 +}
  5795 +
  5796 +static always_inline void gen_op_eveqv (TCGv t0, TCGv t1)
  5797 +{
  5798 + tcg_gen_xor_i64(t0, t0, t1);
  5799 + tcg_gen_not_i64(t0, t0);
  5800 +}
  5801 +
  5802 +static always_inline void gen_op_evorc (TCGv t0, TCGv t1)
  5803 +{
  5804 + tcg_gen_not_i64(t1, t1);
  5805 + tcg_gen_or_i64(t0, t0, t1);
  5806 +}
  5807 +
  5808 +static always_inline void gen_op_evnand (TCGv t0, TCGv t1)
  5809 +{
  5810 + tcg_gen_and_i64(t0, t0, t1);
  5811 + tcg_gen_not_i64(t0, t0);
  5812 +}
  5813 +
  5814 +GEN_SPEOP_TCG_ARITH2(evand);
  5815 +GEN_SPEOP_TCG_ARITH2(evandc);
  5816 +GEN_SPEOP_TCG_ARITH2(evxor);
  5817 +GEN_SPEOP_TCG_ARITH2(evor);
  5818 +GEN_SPEOP_TCG_ARITH2(evnor);
  5819 +GEN_SPEOP_TCG_ARITH2(eveqv);
  5820 +GEN_SPEOP_TCG_ARITH2(evorc);
  5821 +GEN_SPEOP_TCG_ARITH2(evnand);
5760 GEN_SPEOP_ARITH2(evsrwu); 5822 GEN_SPEOP_ARITH2(evsrwu);
5761 GEN_SPEOP_ARITH2(evsrws); 5823 GEN_SPEOP_ARITH2(evsrws);
5762 GEN_SPEOP_ARITH2(evslw); 5824 GEN_SPEOP_ARITH2(evslw);