Commit 3ccacc4a16f01a6dc0e863e2cbdbcc6ba1171e99
1 parent
16c00cb2
Add device save and reset methods to FDC and M48T59
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2665 c046a42c-6fe2-441c-8c8c-71466251a162
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2 changed files
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136 additions
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2 deletions
hw/fdc.c
1 | /* | 1 | /* |
2 | * QEMU Floppy disk emulator (Intel 82078) | 2 | * QEMU Floppy disk emulator (Intel 82078) |
3 | * | 3 | * |
4 | - * Copyright (c) 2003 Jocelyn Mayer | 4 | + * Copyright (c) 2003, 2007 Jocelyn Mayer |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | 7 | * of this software and associated documentation files (the "Software"), to deal |
@@ -485,6 +485,99 @@ static CPUWriteMemoryFunc *fdctrl_mem_write[3] = { | @@ -485,6 +485,99 @@ static CPUWriteMemoryFunc *fdctrl_mem_write[3] = { | ||
485 | fdctrl_write_mem, | 485 | fdctrl_write_mem, |
486 | }; | 486 | }; |
487 | 487 | ||
488 | +static void fd_save (QEMUFile *f, fdrive_t *fd) | ||
489 | +{ | ||
490 | + uint8_t tmp; | ||
491 | + | ||
492 | + tmp = fd->drflags; | ||
493 | + qemu_put_8s(f, &tmp); | ||
494 | + qemu_put_8s(f, &fd->head); | ||
495 | + qemu_put_8s(f, &fd->track); | ||
496 | + qemu_put_8s(f, &fd->sect); | ||
497 | + qemu_put_8s(f, &fd->dir); | ||
498 | + qemu_put_8s(f, &fd->rw); | ||
499 | +} | ||
500 | + | ||
501 | +static void fdc_save (QEMUFile *f, void *opaque) | ||
502 | +{ | ||
503 | + fdctrl_t *s = opaque; | ||
504 | + | ||
505 | + qemu_put_8s(f, &s->state); | ||
506 | + qemu_put_8s(f, &s->dma_en); | ||
507 | + qemu_put_8s(f, &s->cur_drv); | ||
508 | + qemu_put_8s(f, &s->bootsel); | ||
509 | + qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN); | ||
510 | + qemu_put_be32s(f, &s->data_pos); | ||
511 | + qemu_put_be32s(f, &s->data_len); | ||
512 | + qemu_put_8s(f, &s->data_state); | ||
513 | + qemu_put_8s(f, &s->data_dir); | ||
514 | + qemu_put_8s(f, &s->int_status); | ||
515 | + qemu_put_8s(f, &s->eot); | ||
516 | + qemu_put_8s(f, &s->timer0); | ||
517 | + qemu_put_8s(f, &s->timer1); | ||
518 | + qemu_put_8s(f, &s->precomp_trk); | ||
519 | + qemu_put_8s(f, &s->config); | ||
520 | + qemu_put_8s(f, &s->lock); | ||
521 | + qemu_put_8s(f, &s->pwrd); | ||
522 | + fd_save(f, &s->drives[0]); | ||
523 | + fd_save(f, &s->drives[1]); | ||
524 | +} | ||
525 | + | ||
526 | +static int fd_load (QEMUFile *f, fdrive_t *fd) | ||
527 | +{ | ||
528 | + uint8_t tmp; | ||
529 | + | ||
530 | + qemu_get_8s(f, &tmp); | ||
531 | + fd->drflags = tmp; | ||
532 | + qemu_get_8s(f, &fd->head); | ||
533 | + qemu_get_8s(f, &fd->track); | ||
534 | + qemu_get_8s(f, &fd->sect); | ||
535 | + qemu_get_8s(f, &fd->dir); | ||
536 | + qemu_get_8s(f, &fd->rw); | ||
537 | + | ||
538 | + return 0; | ||
539 | +} | ||
540 | + | ||
541 | +static int fdc_load (QEMUFile *f, void *opaque, int version_id) | ||
542 | +{ | ||
543 | + fdctrl_t *s = opaque; | ||
544 | + int ret; | ||
545 | + | ||
546 | + if (version_id != 1) | ||
547 | + return -EINVAL; | ||
548 | + | ||
549 | + qemu_get_8s(f, &s->state); | ||
550 | + qemu_get_8s(f, &s->dma_en); | ||
551 | + qemu_get_8s(f, &s->cur_drv); | ||
552 | + qemu_get_8s(f, &s->bootsel); | ||
553 | + qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN); | ||
554 | + qemu_get_be32s(f, &s->data_pos); | ||
555 | + qemu_get_be32s(f, &s->data_len); | ||
556 | + qemu_get_8s(f, &s->data_state); | ||
557 | + qemu_get_8s(f, &s->data_dir); | ||
558 | + qemu_get_8s(f, &s->int_status); | ||
559 | + qemu_get_8s(f, &s->eot); | ||
560 | + qemu_get_8s(f, &s->timer0); | ||
561 | + qemu_get_8s(f, &s->timer1); | ||
562 | + qemu_get_8s(f, &s->precomp_trk); | ||
563 | + qemu_get_8s(f, &s->config); | ||
564 | + qemu_get_8s(f, &s->lock); | ||
565 | + qemu_get_8s(f, &s->pwrd); | ||
566 | + | ||
567 | + ret = fd_load(f, &s->drives[0]); | ||
568 | + if (ret == 0) | ||
569 | + ret = fd_load(f, &s->drives[1]); | ||
570 | + | ||
571 | + return ret; | ||
572 | +} | ||
573 | + | ||
574 | +static void fdctrl_external_reset(void *opaque) | ||
575 | +{ | ||
576 | + fdctrl_t *s = opaque; | ||
577 | + | ||
578 | + fdctrl_reset(s, 0); | ||
579 | +} | ||
580 | + | ||
488 | fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, | 581 | fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
489 | uint32_t io_base, | 582 | uint32_t io_base, |
490 | BlockDriverState **fds) | 583 | BlockDriverState **fds) |
@@ -525,6 +618,8 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, | @@ -525,6 +618,8 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, | ||
525 | register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl); | 618 | register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl); |
526 | register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl); | 619 | register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl); |
527 | } | 620 | } |
621 | + register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl); | ||
622 | + qemu_register_reset(fdctrl_external_reset, fdctrl); | ||
528 | for (i = 0; i < 2; i++) { | 623 | for (i = 0; i < 2; i++) { |
529 | fd_revalidate(&fdctrl->drives[i]); | 624 | fd_revalidate(&fdctrl->drives[i]); |
530 | } | 625 | } |
hw/m48t59.c
1 | /* | 1 | /* |
2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms | 2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms |
3 | * | 3 | * |
4 | - * Copyright (c) 2003-2005 Jocelyn Mayer | 4 | + * Copyright (c) 2003-2005, 2007 Jocelyn Mayer |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | 7 | * of this software and associated documentation files (the "Software"), to deal |
@@ -575,12 +575,47 @@ static CPUReadMemoryFunc *nvram_read[] = { | @@ -575,12 +575,47 @@ static CPUReadMemoryFunc *nvram_read[] = { | ||
575 | &nvram_readl, | 575 | &nvram_readl, |
576 | }; | 576 | }; |
577 | 577 | ||
578 | +static void m48t59_save(QEMUFile *f, void *opaque) | ||
579 | +{ | ||
580 | + m48t59_t *s = opaque; | ||
581 | + | ||
582 | + qemu_put_8s(f, &s->lock); | ||
583 | + qemu_put_be16s(f, &s->addr); | ||
584 | + qemu_put_buffer(f, s->buffer, s->size); | ||
585 | +} | ||
586 | + | ||
587 | +static int m48t59_load(QEMUFile *f, void *opaque, int version_id) | ||
588 | +{ | ||
589 | + m48t59_t *s = opaque; | ||
590 | + | ||
591 | + if (version_id != 1) | ||
592 | + return -EINVAL; | ||
593 | + | ||
594 | + qemu_get_8s(f, &s->lock); | ||
595 | + qemu_get_be16s(f, &s->addr); | ||
596 | + qemu_get_buffer(f, s->buffer, s->size); | ||
597 | + | ||
598 | + return 0; | ||
599 | +} | ||
600 | + | ||
601 | +static void m48t59_reset(void *opaque) | ||
602 | +{ | ||
603 | + m48t59_t *NVRAM = opaque; | ||
604 | + | ||
605 | + if (NVRAM->alrm_timer != NULL) | ||
606 | + qemu_del_timer(NVRAM->alrm_timer); | ||
607 | + | ||
608 | + if (NVRAM->wd_timer != NULL) | ||
609 | + qemu_del_timer(NVRAM->wd_timer); | ||
610 | +} | ||
611 | + | ||
578 | /* Initialisation routine */ | 612 | /* Initialisation routine */ |
579 | m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base, | 613 | m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base, |
580 | uint32_t io_base, uint16_t size, | 614 | uint32_t io_base, uint16_t size, |
581 | int type) | 615 | int type) |
582 | { | 616 | { |
583 | m48t59_t *s; | 617 | m48t59_t *s; |
618 | + target_ulong save_base; | ||
584 | 619 | ||
585 | s = qemu_mallocz(sizeof(m48t59_t)); | 620 | s = qemu_mallocz(sizeof(m48t59_t)); |
586 | if (!s) | 621 | if (!s) |
@@ -610,5 +645,9 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base, | @@ -610,5 +645,9 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base, | ||
610 | } | 645 | } |
611 | s->lock = 0; | 646 | s->lock = 0; |
612 | 647 | ||
648 | + qemu_register_reset(m48t59_reset, s); | ||
649 | + save_base = mem_base ? mem_base : io_base; | ||
650 | + register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s); | ||
651 | + | ||
613 | return s; | 652 | return s; |
614 | } | 653 | } |