gwj / at91sam9263 · Commits

Commit 3c4c9f9f51599845fba61240aba0f38485df7c14

Authored by ths
1 parent 81442192

Fix PPCEMB for 32bit hosts. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3059 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 6 additions and 6 deletions
target-ppc/cpu.h
  View file @3c4c9f9
... ... @@ -693,7 +693,7 @@ struct CPUPPCState {
693 693 /* temporary fixed-point registers
694 694 * used to emulate 64 bits target on 32 bits hosts
695 695 */
696   - target_ulong t0, t1, t2;
  696 + ppc_gpr_t t0, t1, t2;
697 697 #endif
698 698 ppc_avr_t t0_avr, t1_avr, t2_avr;
699 699  
... ...
target-ppc/exec.h
  View file @3c4c9f9
... ... @@ -43,15 +43,15 @@ register unsigned long T1 asm(AREG2);
43 43 register unsigned long T2 asm(AREG3);
44 44 #endif
45 45 /* We may, sometime, need 64 bits registers on 32 bits target */
46   -#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64)
47   -#define T0_64 T0
48   -#define T1_64 T1
49   -#define T2_64 T2
50   -#else
  46 +#if TARGET_GPR_BITS > HOST_LONG_BITS
51 47 /* no registers can be used */
52 48 #define T0_64 (env->t0)
53 49 #define T1_64 (env->t1)
54 50 #define T2_64 (env->t2)
  51 +#else
  52 +#define T0_64 T0
  53 +#define T1_64 T1
  54 +#define T2_64 T2
55 55 #endif
56 56 /* Provision for Altivec */
57 57 #define T0_avr (env->t0_avr)
... ...