gwj / at91sam9263 · Commits

Commit 3b43004804f01a07e65714e936af9a6cf0c62473

Authored by aurel32
1 parent fad6cb1a

Add vmrg{l,h}{b,h,w} instructions. 

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6163 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 47 additions and 0 deletions
target-ppc/helper.h
  View file @3b43004
@@ -123,6 +123,12 @@ DEF_HELPER_3(vminuw, void, avr, avr, avr) @@ -123,6 +123,12 @@ DEF_HELPER_3(vminuw, void, avr, avr, avr)
123 DEF_HELPER_3(vmaxub, void, avr, avr, avr) 123 DEF_HELPER_3(vmaxub, void, avr, avr, avr)
124 DEF_HELPER_3(vmaxuh, void, avr, avr, avr) 124 DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
125 DEF_HELPER_3(vmaxuw, void, avr, avr, avr) 125 DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
  126 +DEF_HELPER_3(vmrglb, void, avr, avr, avr)
  127 +DEF_HELPER_3(vmrglh, void, avr, avr, avr)
  128 +DEF_HELPER_3(vmrglw, void, avr, avr, avr)
  129 +DEF_HELPER_3(vmrghb, void, avr, avr, avr)
  130 +DEF_HELPER_3(vmrghh, void, avr, avr, avr)
  131 +DEF_HELPER_3(vmrghw, void, avr, avr, avr)
126 132
127 DEF_HELPER_1(efscfsi, i32, i32) 133 DEF_HELPER_1(efscfsi, i32, i32)
128 DEF_HELPER_1(efscfui, i32, i32) 134 DEF_HELPER_1(efscfui, i32, i32)
target-ppc/op_helper.c
  View file @3b43004
@@ -2031,6 +2031,41 @@ VMINMAX(uw, u32) @@ -2031,6 +2031,41 @@ VMINMAX(uw, u32)
2031 #undef VMINMAX_DO 2031 #undef VMINMAX_DO
2032 #undef VMINMAX 2032 #undef VMINMAX
2033 2033
  2034 +#define VMRG_DO(name, element, highp) \
  2035 + void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
  2036 + { \
  2037 + ppc_avr_t result; \
  2038 + int i; \
  2039 + size_t n_elems = ARRAY_SIZE(r->element); \
  2040 + for (i = 0; i < n_elems/2; i++) { \
  2041 + if (highp) { \
  2042 + result.element[i*2+HI_IDX] = a->element[i]; \
  2043 + result.element[i*2+LO_IDX] = b->element[i]; \
  2044 + } else { \
  2045 + result.element[n_elems - i*2 - (1+HI_IDX)] = b->element[n_elems - i - 1]; \
  2046 + result.element[n_elems - i*2 - (1+LO_IDX)] = a->element[n_elems - i - 1]; \
  2047 + } \
  2048 + } \
  2049 + *r = result; \
  2050 + }
  2051 +#if defined(WORDS_BIGENDIAN)
  2052 +#define MRGHI 0
  2053 +#define MRGL0 1
  2054 +#else
  2055 +#define MRGHI 1
  2056 +#define MRGLO 0
  2057 +#endif
  2058 +#define VMRG(suffix, element) \
  2059 + VMRG_DO(mrgl##suffix, element, MRGHI) \
  2060 + VMRG_DO(mrgh##suffix, element, MRGLO)
  2061 +VMRG(b, u8)
  2062 +VMRG(h, u16)
  2063 +VMRG(w, u32)
  2064 +#undef VMRG_DO
  2065 +#undef VMRG
  2066 +#undef MRGHI
  2067 +#undef MRGLO
  2068 +
2034 #undef VECTOR_FOR_INORDER_I 2069 #undef VECTOR_FOR_INORDER_I
2035 #undef HI_IDX 2070 #undef HI_IDX
2036 #undef LO_IDX 2071 #undef LO_IDX
target-ppc/translate.c
  View file @3b43004
@@ -6205,6 +6205,12 @@ GEN_VXFORM(vavguw, 1, 18); @@ -6205,6 +6205,12 @@ GEN_VXFORM(vavguw, 1, 18);
6205 GEN_VXFORM(vavgsb, 1, 20); 6205 GEN_VXFORM(vavgsb, 1, 20);
6206 GEN_VXFORM(vavgsh, 1, 21); 6206 GEN_VXFORM(vavgsh, 1, 21);
6207 GEN_VXFORM(vavgsw, 1, 22); 6207 GEN_VXFORM(vavgsw, 1, 22);
  6208 +GEN_VXFORM(vmrghb, 6, 0);
  6209 +GEN_VXFORM(vmrghh, 6, 1);
  6210 +GEN_VXFORM(vmrghw, 6, 2);
  6211 +GEN_VXFORM(vmrglb, 6, 4);
  6212 +GEN_VXFORM(vmrglh, 6, 5);
  6213 +GEN_VXFORM(vmrglw, 6, 6);
6208 6214
6209 /*** SPE extension ***/ 6215 /*** SPE extension ***/
6210 /* Register moves */ 6216 /* Register moves */