gwj / at91sam9263 · Commits

Commit 39dd32eed2d56fd8f5f5cbdc16ec7fe2faae447a

Authored by aurel32
1 parent b24a39fa

ppc: Convert op_add, op_addi to TCG 

Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 19 additions and 28 deletions
target-ppc/op.c
  View file @39dd32e
... ... @@ -602,12 +602,6 @@ void OPPROTO op_dec_ctr (void)
602 602  
603 603 /*** Integer arithmetic ***/
604 604 /* add */
605   -void OPPROTO op_add (void)
606   -{
607   - T0 += T1;
608   - RETURN();
609   -}
610   -
611 605 void OPPROTO op_check_addo (void)
612 606 {
613 607 xer_ov = (((uint32_t)T2 ^ (uint32_t)T1 ^ UINT32_MAX) &
... ... @@ -664,13 +658,6 @@ void OPPROTO op_adde_64 (void)
664 658 }
665 659 #endif
666 660  
667   -/* add immediate */
668   -void OPPROTO op_addi (void)
669   -{
670   - T0 += (int32_t)PARAM1;
671   - RETURN();
672   -}
673   -
674 661 /* add to minus one extended */
675 662 void OPPROTO op_add_me (void)
676 663 {
... ...
target-ppc/translate.c
  View file @39dd32e
... ... @@ -827,10 +827,14 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
827 827 #endif
828 828  
829 829 /* add add. addo addo. */
  830 +static always_inline void gen_op_add (void)
  831 +{
  832 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  833 +}
830 834 static always_inline void gen_op_addo (void)
831 835 {
832 836 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
833   - gen_op_add();
  837 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
834 838 gen_op_check_addo();
835 839 }
836 840 #if defined(TARGET_PPC64)
... ... @@ -838,7 +842,7 @@ static always_inline void gen_op_addo (void)
838 842 static always_inline void gen_op_addo_64 (void)
839 843 {
840 844 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
841   - gen_op_add();
  845 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
842 846 gen_op_check_addo_64();
843 847 }
844 848 #endif
... ... @@ -847,13 +851,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
847 851 static always_inline void gen_op_addc (void)
848 852 {
849 853 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
850   - gen_op_add();
  854 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
851 855 gen_op_check_addc();
852 856 }
853 857 static always_inline void gen_op_addco (void)
854 858 {
855 859 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
856   - gen_op_add();
  860 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
857 861 gen_op_check_addc();
858 862 gen_op_check_addo();
859 863 }
... ... @@ -861,13 +865,13 @@ static always_inline void gen_op_addco (void)
861 865 static always_inline void gen_op_addc_64 (void)
862 866 {
863 867 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
864   - gen_op_add();
  868 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
865 869 gen_op_check_addc_64();
866 870 }
867 871 static always_inline void gen_op_addco_64 (void)
868 872 {
869 873 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
870   - gen_op_add();
  874 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
871 875 gen_op_check_addc_64();
872 876 gen_op_check_addo_64();
873 877 }
... ... @@ -1022,7 +1026,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1022 1026 } else {
1023 1027 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1024 1028 if (likely(simm != 0))
1025   - gen_op_addi(simm);
  1029 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
1026 1030 }
1027 1031 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1028 1032 }
... ... @@ -1034,7 +1038,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1034 1038 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1035 1039 if (likely(simm != 0)) {
1036 1040 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1037   - gen_op_addi(simm);
  1041 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
1038 1042 #if defined(TARGET_PPC64)
1039 1043 if (ctx->sf_mode)
1040 1044 gen_op_check_addc_64();
... ... @@ -1054,7 +1058,7 @@ GEN_HANDLER2(addic_, &quot;addic.&quot;, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1054 1058 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1055 1059 if (likely(simm != 0)) {
1056 1060 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
1057   - gen_op_addi(simm);
  1061 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
1058 1062 #if defined(TARGET_PPC64)
1059 1063 if (ctx->sf_mode)
1060 1064 gen_op_check_addc_64();
... ... @@ -1078,7 +1082,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1078 1082 } else {
1079 1083 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1080 1084 if (likely(simm != 0))
1081   - gen_op_addi(simm << 16);
  1085 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
1082 1086 }
1083 1087 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1084 1088 }
... ... @@ -2118,7 +2122,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx,
2118 2122 } else {
2119 2123 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
2120 2124 if (likely(simm != 0))
2121   - gen_op_addi(simm);
  2125 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
2122 2126 }
2123 2127 #ifdef DEBUG_MEMORY_ACCESSES
2124 2128 gen_op_print_mem_EA();
... ... @@ -2132,7 +2136,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx)
2132 2136 } else {
2133 2137 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
2134 2138 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
2135   - gen_op_add();
  2139 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2136 2140 }
2137 2141 #ifdef DEBUG_MEMORY_ACCESSES
2138 2142 gen_op_print_mem_EA();
... ... @@ -2331,7 +2335,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2331 2335 gen_addr_imm_index(ctx, 0x0F);
2332 2336 op_ldst(ld);
2333 2337 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
2334   - gen_op_addi(8);
  2338 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
2335 2339 op_ldst(ld);
2336 2340 tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]);
2337 2341 #endif
... ... @@ -2427,7 +2431,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2427 2431 gen_addr_imm_index(ctx, 0x03);
2428 2432 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
2429 2433 op_ldst(std);
2430   - gen_op_addi(8);
  2434 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
2431 2435 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]);
2432 2436 op_ldst(std);
2433 2437 #endif
... ... @@ -5346,7 +5350,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5346 5350 } else {
5347 5351 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5348 5352 if (likely(simm != 0))
5349   - gen_op_addi(simm << sh);
  5353 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh);
5350 5354 }
5351 5355 }
5352 5356  
... ...