gwj / at91sam9263 · Commits

Commit 397e923f7f78e99bc547b0a730c225d78dfe878b

Authored by pbrook
1 parent 4dbed897

Remove debug output. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1990 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 2 additions and 4 deletions
target-sh4/op_helper.c
  View file @397e923
@@ -135,7 +135,7 @@ void helper_div1_T0_T1(void) @@ -135,7 +135,7 @@ void helper_div1_T0_T1(void)
135 uint32_t tmp0, tmp2; 135 uint32_t tmp0, tmp2;
136 uint8_t old_q, tmp1 = 0xff; 136 uint8_t old_q, tmp1 = 0xff;
137 137
138 - printf("div1 T0=0x%08x T1=0x%08x M=%d Q=%d T=%d\n", T0, T1, M, Q, T); 138 + //printf("div1 T0=0x%08x T1=0x%08x M=%d Q=%d T=%d\n", T0, T1, M, Q, T);
139 old_q = Q; 139 old_q = Q;
140 if ((0x80000000 & T1) != 0) 140 if ((0x80000000 & T1) != 0)
141 SETQ; 141 SETQ;
@@ -234,7 +234,7 @@ void helper_div1_T0_T1(void) @@ -234,7 +234,7 @@ void helper_div1_T0_T1(void)
234 SETT; 234 SETT;
235 else 235 else
236 CLRT; 236 CLRT;
237 - printf("Output: T1=0x%08x M=%d Q=%d T=%d\n", T1, M, Q, T); 237 + //printf("Output: T1=0x%08x M=%d Q=%d T=%d\n", T1, M, Q, T);
238 } 238 }
239 239
240 void helper_dmulsl_T0_T1() 240 void helper_dmulsl_T0_T1()
target-sh4/translate.c
  View file @397e923
@@ -247,7 +247,6 @@ void decode_opc(DisasContext * ctx) @@ -247,7 +247,6 @@ void decode_opc(DisasContext * ctx)
247 #endif 247 #endif
248 switch (ctx->opcode) { 248 switch (ctx->opcode) {
249 case 0x0019: /* div0u */ 249 case 0x0019: /* div0u */
250 - printf("div0u\n");  
251 gen_op_div0u(); 250 gen_op_div0u();
252 return; 251 return;
253 case 0x000b: /* rts */ 252 case 0x000b: /* rts */
@@ -509,7 +508,6 @@ void decode_opc(DisasContext * ctx) @@ -509,7 +508,6 @@ void decode_opc(DisasContext * ctx)
509 gen_op_cmp_str_T0_T1(); 508 gen_op_cmp_str_T0_T1();
510 return; 509 return;
511 case 0x2007: /* div0s Rm,Rn */ 510 case 0x2007: /* div0s Rm,Rn */
512 - printf("div0s\n");  
513 gen_op_movl_rN_T0(REG(B7_4)); 511 gen_op_movl_rN_T0(REG(B7_4));
514 gen_op_movl_rN_T1(REG(B11_8)); 512 gen_op_movl_rN_T1(REG(B11_8));
515 gen_op_div0s_T0_T1(); 513 gen_op_div0s_T0_T1();