Commit 3947c3d505e0b5f6586ec43b03b4affb9fb06b56
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AT91 PES Development Board
The board scheme is available at http://support.dce.felk.cvut.cz/e-kurzy/file.php/19/cviceni/Schema.pdf Only the AT91SAM7X microcontroller, rotary encoder, matrix keyboard and their connections are implemented. Signed-off-by: Filip Navara <filip.navara@gmail.com>
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1 deletions
Makefile.target
| ... | ... | @@ -432,7 +432,7 @@ obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o |
| 432 | 432 | obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o |
| 433 | 433 | obj-arm-y += syborg_virtio.o |
| 434 | 434 | obj-arm-y += at91_aic.o at91_dbgu.o at91_pio.o at91_pit.o at91_pmc.o at91_rtt.o |
| 435 | -obj-arm-y += at91_rstc.o at91_intor.o at91_tc.o at91_emac.o | |
| 435 | +obj-arm-y += at91_rstc.o at91_intor.o at91_tc.o at91_emac.o at91pes.o | |
| 436 | 436 | obj-arm-y += gpio_rotary.o gpio_keypad.o |
| 437 | 437 | |
| 438 | 438 | ifeq ($(TARGET_BASE_ARCH), arm) | ... | ... |
hw/at91pes.c
0 → 100644
| 1 | +/* | |
| 2 | + * AT91 PES Development Board | |
| 3 | + * | |
| 4 | + * Copyright (c) 2009 Filip Navara | |
| 5 | + * | |
| 6 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 7 | + * of this software and associated documentation files (the "Software"), to deal | |
| 8 | + * in the Software without restriction, including without limitation the rights | |
| 9 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 10 | + * copies of the Software, and to permit persons to whom the Software is | |
| 11 | + * furnished to do so, subject to the following conditions: | |
| 12 | + * | |
| 13 | + * The above copyright notice and this permission notice shall be included in | |
| 14 | + * all copies or substantial portions of the Software. | |
| 15 | + * | |
| 16 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 20 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 21 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 22 | + * THE SOFTWARE. | |
| 23 | + */ | |
| 24 | + | |
| 25 | +#include "sysbus.h" | |
| 26 | +#include "boards.h" | |
| 27 | +#include "arm-misc.h" | |
| 28 | +#include "sysemu.h" | |
| 29 | +#include "net.h" | |
| 30 | + | |
| 31 | +static void at91pes_init(ram_addr_t ram_size, | |
| 32 | + const char *boot_device, | |
| 33 | + const char *kernel_filename, const char *kernel_cmdline, | |
| 34 | + const char *initrd_filename, const char *cpu_model) | |
| 35 | +{ | |
| 36 | + struct arm_boot_info at91pes_binfo; | |
| 37 | + CPUState *env; | |
| 38 | + qemu_irq *cpu_pic; | |
| 39 | + qemu_irq pic[32]; | |
| 40 | + qemu_irq pic1[32]; | |
| 41 | + ram_addr_t ram_addr; | |
| 42 | + DeviceState *dev; | |
| 43 | + DeviceState *pioa; | |
| 44 | + DeviceState *piob; | |
| 45 | + DeviceState *pmc; | |
| 46 | + DeviceState *pit; | |
| 47 | + uint32_t keys[] = { | |
| 48 | + 2 /* 1 */, 3 /* 2 */, 4 /* 3 */, 30 /* A */, | |
| 49 | + 5 /* 4 */, 6 /* 5 */, 7 /* 6 */, 48 /* B */, | |
| 50 | + 8 /* 7 */, 9 /* 8 */, 10 /* 9 */, 46 /* C */, | |
| 51 | + 42 /* LShift */, 11 /* 0 */, 12 /* - */, 32 /* D */ | |
| 52 | + }; | |
| 53 | + int i; | |
| 54 | + | |
| 55 | + if (!cpu_model) | |
| 56 | + cpu_model = "arm7tdmi"; | |
| 57 | + env = cpu_init(cpu_model); | |
| 58 | + if (!env) { | |
| 59 | + fprintf(stderr, "Unable to find CPU definition\n"); | |
| 60 | + exit(1); | |
| 61 | + } | |
| 62 | + | |
| 63 | + /* RAM at address zero. */ | |
| 64 | + ram_addr = qemu_ram_alloc(ram_size); | |
| 65 | + cpu_register_physical_memory(0, 0x100000, ram_addr | IO_MEM_RAM); | |
| 66 | + cpu_register_physical_memory(0x200000, ram_size, ram_addr | IO_MEM_RAM); | |
| 67 | + | |
| 68 | + cpu_pic = arm_pic_init_cpu(env); | |
| 69 | + dev = sysbus_create_varargs("at91,aic", 0xFFFFF000, | |
| 70 | + cpu_pic[ARM_PIC_CPU_IRQ], | |
| 71 | + cpu_pic[ARM_PIC_CPU_FIQ], | |
| 72 | + NULL); | |
| 73 | + for (i = 0; i < 32; i++) { | |
| 74 | + pic[i] = qdev_get_gpio_in(dev, i); | |
| 75 | + } | |
| 76 | + | |
| 77 | + dev = sysbus_create_simple("at91,intor", -1, pic[1]); | |
| 78 | + for (i = 0; i < 32; i++) { | |
| 79 | + pic1[i] = qdev_get_gpio_in(dev, i); | |
| 80 | + } | |
| 81 | + | |
| 82 | + sysbus_create_simple("at91,dbgu", 0xFFFFF200, pic1[0]); | |
| 83 | + pmc = sysbus_create_simple("at91,pmc", 0xFFFFFC00, pic1[1]); | |
| 84 | + sysbus_create_varargs("at91,rstc", 0xFFFFFD00, NULL); | |
| 85 | + pioa = sysbus_create_simple("at91,pio", 0xFFFFF400, pic[2]); | |
| 86 | + piob = sysbus_create_simple("at91,pio", 0xFFFFF600, pic[3]); | |
| 87 | + sysbus_create_simple("at91,rtt", 0xFFFFFD20, pic1[2]); | |
| 88 | + pit = sysbus_create_simple("at91,pit", 0xFFFFFD30, pic1[3]); | |
| 89 | + sysbus_create_varargs("at91,tc", 0xFFFA0000, pic[12], pic[13], pic[14], NULL); | |
| 90 | + | |
| 91 | + qemu_check_nic_model(&nd_table[0], "at91"); | |
| 92 | + dev = qdev_create(NULL, "at91,emac"); | |
| 93 | + dev->nd = &nd_table[0]; | |
| 94 | + qdev_init(dev); | |
| 95 | + sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xFFFDC000); | |
| 96 | + sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[16]); | |
| 97 | + | |
| 98 | + dev = qdev_create(NULL, "gpio,keypad"); | |
| 99 | + qdev_prop_set_ptr(dev, "keys", keys); | |
| 100 | + qdev_init(dev); | |
| 101 | + for (i = 0; i < 4; i++) { | |
| 102 | + qdev_connect_gpio_out(pioa, 21 + i, qdev_get_gpio_in(dev, 4 + i)); | |
| 103 | + qdev_connect_gpio_out(dev, 4 + i, qdev_get_gpio_in(pioa, 21 + i)); | |
| 104 | + } | |
| 105 | + for (i = 0; i < 2; i++) { | |
| 106 | + qdev_connect_gpio_out(pioa, 26 - i, qdev_get_gpio_in(dev, 2 + i)); | |
| 107 | + qdev_connect_gpio_out(dev, 2 + i, qdev_get_gpio_in(pioa, 26 - i)); | |
| 108 | + qdev_connect_gpio_out(pioa, 30 - i, qdev_get_gpio_in(dev, i)); | |
| 109 | + qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pioa, 30 - i)); | |
| 110 | + } | |
| 111 | + | |
| 112 | + dev = qdev_create(NULL, "gpio,rotary"); | |
| 113 | + qdev_prop_set_uint32(dev, "key-left", 0xcb); | |
| 114 | + qdev_prop_set_uint32(dev, "key-right", 0xcd); | |
| 115 | + qdev_init(dev); | |
| 116 | + qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(piob, 22)); | |
| 117 | + qdev_connect_gpio_out(dev, 1, qdev_get_gpio_in(piob, 23)); | |
| 118 | + | |
| 119 | + at91pes_binfo.ram_size = ram_size; | |
| 120 | + at91pes_binfo.kernel_filename = kernel_filename; | |
| 121 | + at91pes_binfo.kernel_cmdline = kernel_cmdline; | |
| 122 | + at91pes_binfo.initrd_filename = initrd_filename; | |
| 123 | + at91pes_binfo.board_id = 0; | |
| 124 | + arm_load_kernel(env, &at91pes_binfo); | |
| 125 | +} | |
| 126 | + | |
| 127 | +static QEMUMachine at91pes_machine = { | |
| 128 | + .name = "at91pes", | |
| 129 | + .desc = "Atmel AT91SAM7X PES Development Board", | |
| 130 | + .init = at91pes_init, | |
| 131 | +}; | |
| 132 | + | |
| 133 | +static void at91pes_machine_init(void) | |
| 134 | +{ | |
| 135 | + qemu_register_machine(&at91pes_machine); | |
| 136 | +} | |
| 137 | + | |
| 138 | +machine_init(at91pes_machine_init); | ... | ... |