gwj / at91sam9263 · Commits

Commit 3945462805beb52cdc3e42eff948afbe2e7c4683

Authored by ths
1 parent f730fd27

Simplify mips branch handling. Retire T2 from use. Use TCG for branches. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4320 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 55 additions and 77 deletions
target-mips/cpu.h
  View file @3945462
... ... @@ -148,7 +148,6 @@ struct CPUMIPSState {
148 148 #if TARGET_LONG_BITS > HOST_LONG_BITS
149 149 target_ulong t0;
150 150 target_ulong t1;
151   - target_ulong t2;
152 151 #endif
153 152 target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC];
154 153 target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC];
... ...
target-mips/exec.h
  View file @3945462
... ... @@ -13,11 +13,9 @@ register struct CPUMIPSState *env asm(AREG0);
13 13 #if TARGET_LONG_BITS > HOST_LONG_BITS
14 14 #define T0 (env->t0)
15 15 #define T1 (env->t1)
16   -#define T2 (env->t2)
17 16 #else
18   -register target_ulong T0 asm(AREG1);
19   -register target_ulong T1 asm(AREG2);
20   -register target_ulong T2 asm(AREG3);
  17 +register target_ulong T0 asm(AREG2);
  18 +register target_ulong T1 asm(AREG3);
21 19 #endif
22 20  
23 21 #if defined (USE_HOST_FLOAT_REGS)
... ...
target-mips/op.c
  View file @3945462
... ... @@ -247,12 +247,6 @@
247 247 #include "fop_template.c"
248 248 #undef FTN
249 249  
250   -void op_dup_T0 (void)
251   -{
252   - T2 = T0;
253   - FORCE_RET();
254   -}
255   -
256 250 void op_load_HI (void)
257 251 {
258 252 T0 = env->HI[env->current_tc][PARAM1];
... ... @@ -1096,19 +1090,13 @@ OP_COND(ltz, (target_long)T0 < 0);
1096 1090 /* Branch to register */
1097 1091 void op_save_breg_target (void)
1098 1092 {
1099   - env->btarget = T2;
1100   - FORCE_RET();
1101   -}
1102   -
1103   -void op_restore_breg_target (void)
1104   -{
1105   - T2 = env->btarget;
  1093 + env->btarget = T1;
1106 1094 FORCE_RET();
1107 1095 }
1108 1096  
1109 1097 void op_breg (void)
1110 1098 {
1111   - env->PC[env->current_tc] = T2;
  1099 + env->PC[env->current_tc] = env->btarget;
1112 1100 FORCE_RET();
1113 1101 }
1114 1102  
... ... @@ -1129,25 +1117,13 @@ void op_save_btarget64 (void)
1129 1117 /* Conditional branch */
1130 1118 void op_set_bcond (void)
1131 1119 {
1132   - T2 = T0;
1133   - FORCE_RET();
1134   -}
1135   -
1136   -void op_save_bcond (void)
1137   -{
1138   - env->bcond = T2;
1139   - FORCE_RET();
1140   -}
1141   -
1142   -void op_restore_bcond (void)
1143   -{
1144   - T2 = env->bcond;
  1120 + env->bcond = T0;
1145 1121 FORCE_RET();
1146 1122 }
1147 1123  
1148   -void op_jnz_T2 (void)
  1124 +void op_jnz_bcond (void)
1149 1125 {
1150   - if (T2)
  1126 + if (env->bcond)
1151 1127 GOTO_LABEL_PARAM(1);
1152 1128 FORCE_RET();
1153 1129 }
... ... @@ -3116,12 +3092,6 @@ void op_debug (void)
3116 3092 FORCE_RET();
3117 3093 }
3118 3094  
3119   -void op_set_lladdr (void)
3120   -{
3121   - env->CP0_LLAddr = T2;
3122   - FORCE_RET();
3123   -}
3124   -
3125 3095 void debug_pre_eret (void);
3126 3096 void debug_post_eret (void);
3127 3097 void op_eret (void)
... ...
target-mips/op_template.c
  View file @3945462
... ... @@ -43,12 +43,6 @@ void glue(op_store_T1_gpr_gpr, REG) (void)
43 43 FORCE_RET();
44 44 }
45 45  
46   -void glue(op_load_gpr_T2_gpr, REG) (void)
47   -{
48   - T2 = env->gpr[env->current_tc][REG];
49   - FORCE_RET();
50   -}
51   -
52 46  
53 47 void glue(op_load_srsgpr_T0_gpr, REG) (void)
54 48 {
... ... @@ -78,7 +72,6 @@ void glue(op_store_T0_srsgpr_gpr, REG) (void)
78 72  
79 73 SET_RESET(T0, _T0)
80 74 SET_RESET(T1, _T1)
81   -SET_RESET(T2, _T2)
82 75  
83 76 #undef SET_RESET
84 77  
... ... @@ -92,7 +85,6 @@ SET_RESET(T2, _T2)
92 85  
93 86 SET64(T0, _T0)
94 87 SET64(T1, _T1)
95   -SET64(T2, _T2)
96 88  
97 89 #undef SET64
98 90  
... ...
target-mips/translate.c
  View file @3945462
... ... @@ -421,6 +421,8 @@ enum {
421 421 OPC_NMSUB_PS= 0x3E | OPC_CP3,
422 422 };
423 423  
  424 +/* global register indices */
  425 +static TCGv cpu_env, current_tc_regs, cpu_T[2];
424 426  
425 427 const unsigned char *regnames[] =
426 428 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
... ... @@ -448,7 +450,6 @@ static always_inline void func(int n) \
448 450 /* General purpose registers moves */
449 451 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
450 452 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
451   -GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
452 453  
453 454 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
454 455 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
... ... @@ -599,15 +600,6 @@ do { \
599 600 } \
600 601 } while (0)
601 602  
602   -#define GEN_LOAD_REG_T2(Rn) \
603   -do { \
604   - if (Rn == 0) { \
605   - gen_op_reset_T2(); \
606   - } else { \
607   - gen_op_load_gpr_T2(Rn); \
608   - } \
609   -} while (0)
610   -
611 603 #define GEN_LOAD_SRSREG_TN(Tn, Rn) \
612 604 do { \
613 605 if (Rn == 0) { \
... ... @@ -714,14 +706,9 @@ static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
714 706 ctx->saved_hflags = ctx->hflags;
715 707 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
716 708 case MIPS_HFLAG_BR:
717   - gen_op_save_breg_target();
718 709 break;
719 710 case MIPS_HFLAG_BC:
720   - gen_op_save_bcond();
721   - /* fall through */
722 711 case MIPS_HFLAG_BL:
723   - /* bcond was already saved by the BL insn */
724   - /* fall through */
725 712 case MIPS_HFLAG_B:
726 713 gen_save_btarget(ctx->btarget);
727 714 break;
... ... @@ -734,15 +721,11 @@ static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
734 721 ctx->saved_hflags = ctx->hflags;
735 722 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
736 723 case MIPS_HFLAG_BR:
737   - gen_op_restore_breg_target();
738   - break;
739   - case MIPS_HFLAG_B:
740   - ctx->btarget = env->btarget;
741 724 break;
742 725 case MIPS_HFLAG_BC:
743 726 case MIPS_HFLAG_BL:
  727 + case MIPS_HFLAG_B:
744 728 ctx->btarget = env->btarget;
745   - gen_op_restore_bcond();
746 729 break;
747 730 }
748 731 }
... ... @@ -1770,6 +1753,19 @@ static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong des
1770 1753 }
1771 1754 }
1772 1755  
  1756 +static inline void tcg_gen_set_bcond(void)
  1757 +{
  1758 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
  1759 +}
  1760 +
  1761 +static inline void tcg_gen_jnz_bcond(int label)
  1762 +{
  1763 + int r_tmp = tcg_temp_new(TCG_TYPE_TL);
  1764 +
  1765 + tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, bcond));
  1766 + tcg_gen_brcond_tl(TCG_COND_NE, r_tmp, tcg_const_i32(0), label);
  1767 +}
  1768 +
1773 1769 /* Branches (before delay slot) */
1774 1770 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1775 1771 int rs, int rt, int32_t offset)
... ... @@ -1838,7 +1834,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1838 1834 generate_exception(ctx, EXCP_RI);
1839 1835 return;
1840 1836 }
1841   - GEN_LOAD_REG_T2(rs);
  1837 + GEN_LOAD_REG_T1(rs);
  1838 + gen_op_save_breg_target();
1842 1839 break;
1843 1840 default:
1844 1841 MIPS_INVAL("branch/jump");
... ... @@ -1983,7 +1980,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1983 1980 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
1984 1981 not_likely:
1985 1982 ctx->hflags |= MIPS_HFLAG_BC;
1986   - gen_op_set_bcond();
  1983 + tcg_gen_set_bcond();
1987 1984 break;
1988 1985 case OPC_BLTZALL:
1989 1986 gen_op_ltz();
... ... @@ -1991,8 +1988,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1991 1988 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
1992 1989 likely:
1993 1990 ctx->hflags |= MIPS_HFLAG_BL;
1994   - gen_op_set_bcond();
1995   - gen_op_save_bcond();
  1991 + tcg_gen_set_bcond();
1996 1992 break;
1997 1993 default:
1998 1994 MIPS_INVAL("conditional branch/jump");
... ... @@ -4863,8 +4859,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
4863 4859 opn = "bc1tl";
4864 4860 likely:
4865 4861 ctx->hflags |= MIPS_HFLAG_BL;
4866   - gen_op_set_bcond();
4867   - gen_op_save_bcond();
  4862 + tcg_gen_set_bcond();
4868 4863 break;
4869 4864 case OPC_BC1FANY2:
4870 4865 gen_op_bc1any2f(cc);
... ... @@ -4883,7 +4878,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
4883 4878 opn = "bc1any4t";
4884 4879 not_likely:
4885 4880 ctx->hflags |= MIPS_HFLAG_BC;
4886   - gen_op_set_bcond();
  4881 + tcg_gen_set_bcond();
4887 4882 break;
4888 4883 default:
4889 4884 MIPS_INVAL(opn);
... ... @@ -6056,7 +6051,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6056 6051 /* Handle blikely not taken case */
6057 6052 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
6058 6053 l1 = gen_new_label();
6059   - gen_op_jnz_T2(l1);
  6054 + tcg_gen_jnz_bcond(l1);
6060 6055 gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
6061 6056 gen_goto_tb(ctx, 1, ctx->pc + 4);
6062 6057 gen_set_label(l1);
... ... @@ -6612,7 +6607,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6612 6607 {
6613 6608 int l1;
6614 6609 l1 = gen_new_label();
6615   - gen_op_jnz_T2(l1);
  6610 + tcg_gen_jnz_bcond(l1);
6616 6611 gen_goto_tb(ctx, 1, ctx->pc + 4);
6617 6612 gen_set_label(l1);
6618 6613 gen_goto_tb(ctx, 0, ctx->btarget);
... ... @@ -6877,6 +6872,29 @@ void cpu_dump_state (CPUState *env, FILE *f,
6877 6872 #endif
6878 6873 }
6879 6874  
  6875 +static void mips_tcg_init(void)
  6876 +{
  6877 + static int inited;
  6878 +
  6879 + /* Initialize various static tables. */
  6880 + if (inited)
  6881 + return;
  6882 +
  6883 + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
  6884 + current_tc_regs = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG1, "current_tc_regs");
  6885 +#if TARGET_LONG_BITS > HOST_LONG_BITS
  6886 + cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
  6887 + TCG_AREG0, offsetof(CPUState, t0), "T0");
  6888 + cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
  6889 + TCG_AREG0, offsetof(CPUState, t1), "T1");
  6890 +#else
  6891 + cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T0");
  6892 + cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T1");
  6893 +#endif
  6894 +
  6895 + inited = 1;
  6896 +}
  6897 +
6880 6898 #include "translate_init.c"
6881 6899  
6882 6900 CPUMIPSState *cpu_mips_init (const char *cpu_model)
... ... @@ -6894,6 +6912,7 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model)
6894 6912  
6895 6913 cpu_exec_init(env);
6896 6914 env->cpu_model_str = cpu_model;
  6915 + mips_tcg_init();
6897 6916 cpu_reset(env);
6898 6917 return env;
6899 6918 }
... ...