gwj / at91sam9263 · Commits

Commit 38121543c7e614fed740c5d902e7ea986ddb2fb8

Authored by ths
1 parent 7524c84d

MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers 

are implemented.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2589 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 9 additions and 2 deletions
target-mips/translate.c
  View file @3812154
... ... @@ -1375,7 +1375,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1375 1375 if (ctx->hflags & MIPS_HFLAG_BMASK) {
1376 1376 if (loglevel & CPU_LOG_TB_IN_ASM) {
1377 1377 fprintf(logfile,
1378   - "undefined branch in delay slot at pc 0x%08x\n", ctx->pc);
  1378 + "undefined branch in delay slot at PC " TARGET_FMT_lx "\n",
  1379 + ctx->pc);
1379 1380 }
1380 1381 MIPS_INVAL("branch/jump in bdelay slot");
1381 1382 generate_exception(ctx, EXCP_RI);
... ... @@ -4841,9 +4842,15 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
4841 4842 }
4842 4843 GEN_STORE_TN_REG(rt, T0);
4843 4844 break;
4844   - /* Shadow registers (not implemented). */
4845 4845 case OPC_RDPGPR:
4846 4846 case OPC_WRPGPR:
  4847 + if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) {
  4848 + /* Shadow registers not implemented. */
  4849 + GEN_LOAD_REG_TN(T0, rt);
  4850 + GEN_STORE_TN_REG(rd, T0);
  4851 + } else
  4852 + generate_exception(ctx, EXCP_RI);
  4853 + break;
4847 4854 default:
4848 4855 generate_exception(ctx, EXCP_RI);
4849 4856 break;
... ...