Reorganise Sun4m to allow other machine types

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2570 c046a42c-6fe2-441c-8c8c-71466251a162

Reorganise Sun4m to allow other machine types
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2570 c046a42c-6fe2-441c-8c8c-71466251a162
blueswir1
1 parent 8a08f9a8
Showing 3 changed files with 135 additions and 64 deletions
hw/sun4m.c
vl.c
vl.h
@@ -23,43 +23,44 @@
  */
 #include "vl.h"
+/*
+ * Sun4m architecture was used in the following machines:
+ *
+ * SPARCserver 6xxMP/xx
+ * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
+ * SPARCstation LX/ZX (4/30)
+ * SPARCstation Voyager
+ * SPARCstation 10/xx, SPARCserver 10/xx
+ * SPARCstation 5, SPARCserver 5
+ * SPARCstation 20/xx, SPARCserver 20
+ * SPARCstation 4
+ *
+ * See for example: http://www.sunhelp.org/faq/sunref1.html
+ */
+
 #define KERNEL_LOAD_ADDR     0x00004000
 #define CMDLINE_ADDR         0x007ff000
 #define INITRD_LOAD_ADDR     0x00800000
 #define PROM_SIZE_MAX        (256 * 1024)
 #define PROM_ADDR	     0xffd00000
 #define PROM_FILENAME	     "openbios-sparc32"
-#define PHYS_JJ_EEPROM	0x71200000	/* m48t08 */
-#define PHYS_JJ_IDPROM_OFF	0x1FD8
-#define PHYS_JJ_EEPROM_SIZE	0x2000
-// IRQs are not PIL ones, but master interrupt controller register
-// bits
-#define PHYS_JJ_IOMMU	0x10000000	/* I/O MMU */
-#define PHYS_JJ_TCX_FB	0x50000000	/* TCX frame buffer */
-#define PHYS_JJ_SLAVIO	0x70000000	/* Slavio base */
-#define PHYS_JJ_DMA     0x78400000      /* DMA controller */
-#define PHYS_JJ_ESP     0x78800000      /* ESP SCSI */
-#define PHYS_JJ_ESP_IRQ    18
-#define PHYS_JJ_LE      0x78C00000      /* Lance ethernet */
-#define PHYS_JJ_LE_IRQ     16
-#define PHYS_JJ_CLOCK	0x71D00000      /* Per-CPU timer/counter, L14 */
-#define PHYS_JJ_CLOCK_IRQ  7
-#define PHYS_JJ_CLOCK1	0x71D10000      /* System timer/counter, L10 */
-#define PHYS_JJ_CLOCK1_IRQ 19
-#define PHYS_JJ_INTR0	0x71E00000	/* Per-CPU interrupt control registers */
-#define PHYS_JJ_INTR_G	0x71E10000	/* Master interrupt control registers */
-#define PHYS_JJ_MS_KBD	0x71000000	/* Mouse and keyboard */
-#define PHYS_JJ_MS_KBD_IRQ    14
-#define PHYS_JJ_SER	0x71100000	/* Serial */
-#define PHYS_JJ_SER_IRQ    15
-#define PHYS_JJ_FDC	0x71400000	/* Floppy */
-#define PHYS_JJ_FLOPPY_IRQ 22
-#define PHYS_JJ_ME_IRQ 30		/* Module error, power fail */
-#define PHYS_JJ_CS      0x6c000000      /* Crystal CS4231 */
-#define PHYS_JJ_CS_IRQ  5
 #define MAX_CPUS 16
+struct hwdef {
+    target_ulong iommu_base, slavio_base;
+    target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
+    target_ulong fd_base;
+    target_ulong dma_base, esp_base, le_base;
+    target_ulong tcx_base, cs_base;
+    long vram_size, nvram_size;
+    // IRQ numbers are not PIL ones, but master interrupt controller register
+    // bit numbers
+    int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
+    int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
+    int machine_id; // For NVRAM
+};
+
 /* TSC handling */
 uint64_t cpu_get_tsc()
@@ -122,7 +123,8 @@ extern int nographic;
 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
 		       int boot_device, uint32_t RAM_size,
 		       uint32_t kernel_size,
-		       int width, int height, int depth)
+		       int width, int height, int depth,
+                       int machine_id)
 {
     unsigned char tmp = 0;
     int i, j;
@@ -151,7 +153,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
     // Sun4m specific use
     i = 0x1fd8;
     m48t59_write(nvram, i++, 0x01);
-    m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
+    m48t59_write(nvram, i++, machine_id);
     j = 0;
     m48t59_write(nvram, i++, macaddr[j++]);
     m48t59_write(nvram, i++, macaddr[j++]);
@@ -207,25 +209,16 @@ static void main_cpu_reset(void *opaque)
     cpu_reset(env);
 }
-/* Sun4m hardware initialisation */
-static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
-                       DisplayState *ds, const char **fd_filename, int snapshot,
-                       const char *kernel_filename, const char *kernel_cmdline,
-                       const char *initrd_filename, const char *cpu_model)
+static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
+                          DisplayState *ds, const char *cpu_model)
+
 {
     CPUState *env, *envs[MAX_CPUS];
-    char buf[1024];
-    int ret, linux_boot;
     unsigned int i;
-    long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
     void *iommu, *dma, *main_esp, *main_lance = NULL;
     const sparc_def_t *def;
-    linux_boot = (kernel_filename != NULL);
-
     /* init CPUs */
-    if (cpu_model == NULL)
-        cpu_model = "Fujitsu MB86904";
     sparc_find_by_name(cpu_model, &def);
     if (def == NULL) {
         fprintf(stderr, "Unable to find Sparc CPU definition\n");
@@ -243,34 +236,40 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
     /* allocate RAM */
     cpu_register_physical_memory(0, ram_size, 0);
-    iommu = iommu_init(PHYS_JJ_IOMMU);
-    slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
+    iommu = iommu_init(hwdef->iommu_base);
+    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
+                                       hwdef->intctl_base + 0x10000);
     for(i = 0; i < smp_cpus; i++) {
         slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
     }
-    dma = sparc32_dma_init(PHYS_JJ_DMA, PHYS_JJ_ESP_IRQ, PHYS_JJ_LE_IRQ, iommu, slavio_intctl);
+    dma = sparc32_dma_init(hwdef->dma_base, hwdef->esp_irq,
+                           hwdef->le_irq, iommu, slavio_intctl);
-    tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
+    tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
+             hwdef->vram_size, graphic_width, graphic_height);
     if (nd_table[0].vlan) {
         if (nd_table[0].model == NULL
             || strcmp(nd_table[0].model, "lance") == 0) {
-            main_lance = lance_init(&nd_table[0], PHYS_JJ_LE, dma);
+            main_lance = lance_init(&nd_table[0], hwdef->le_base, dma);
         } else {
             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
             exit (1);
         }
     }
-    nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
+    nvram = m48t59_init(0, hwdef->nvram_base, 0, hwdef->nvram_size, 8);
     for (i = 0; i < MAX_CPUS; i++) {
-        slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
+        slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE,
+                          hwdef->clock_irq, 0, i);
     }
-    slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
-    slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
+    slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2,
+                      (unsigned int)-1);
+    slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq);
     // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
     // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
-    slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
-    fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
-    main_esp = esp_init(bs_table, PHYS_JJ_ESP, dma);
+    slavio_serial_init(hwdef->serial_base, hwdef->ser_irq,
+                       serial_hds[1], serial_hds[0]);
+    fdctrl_init(hwdef->fd_irq, 0, 1, hwdef->fd_base, fd_table);
+    main_esp = esp_init(bs_table, hwdef->esp_base, dma);
     for (i = 0; i < MAX_DISKS; i++) {
         if (bs_table[i]) {
@@ -278,9 +277,23 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
         }
     }
-    slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
-    cs_init(PHYS_JJ_CS, PHYS_JJ_CS_IRQ, slavio_intctl);
+    slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq);
+    cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
     sparc32_dma_set_reset_data(dma, main_esp, main_lance);
+}
+
+static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,
+                              const char *kernel_filename,
+                              const char *kernel_cmdline,
+                              const char *initrd_filename,
+                              int machine_id)
+{
+    int ret, linux_boot;
+    char buf[1024];
+    unsigned int i;
+    long prom_offset, initrd_size, kernel_size;
+
+    linux_boot = (kernel_filename != NULL);
     prom_offset = ram_size + vram_size;
     cpu_register_physical_memory(PROM_ADDR, 
@@ -329,11 +342,69 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
 	    }
         }
     }
-    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
+    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
+               boot_device, ram_size, kernel_size, graphic_width,
+               graphic_height, graphic_depth, machine_id);
+}
+
+static const struct hwdef hwdefs[] = {
+    /* SS-5 */
+    {
+        .iommu_base   = 0x10000000,
+        .tcx_base     = 0x50000000,
+        .cs_base      = 0x6c000000,
+        .slavio_base  = 0x71000000,
+        .ms_kb_base   = 0x71000000,
+        .serial_base  = 0x71100000,
+        .nvram_base   = 0x71200000,
+        .fd_base      = 0x71400000,
+        .counter_base = 0x71d00000,
+        .intctl_base  = 0x71e00000,
+        .dma_base     = 0x78400000,
+        .esp_base     = 0x78800000,
+        .le_base      = 0x78c00000,
+        .vram_size    = 0x00100000,
+        .nvram_size   = 0x2000,
+        .esp_irq = 18,
+        .le_irq = 16,
+        .clock_irq = 7,
+        .clock1_irq = 19,
+        .ms_kb_irq = 14,
+        .ser_irq = 15,
+        .fd_irq = 22,
+        .me_irq = 30,
+        .cs_irq = 5,
+        .machine_id = 0x80,
+    },
+};
+
+static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds,
+                              const char *kernel_filename, const char *kernel_cmdline,
+                              const char *initrd_filename, const char *cpu_model,
+                              unsigned int machine)
+{
+    sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);
+
+    sun4m_load_kernel(hwdefs[machine].vram_size, ram_size, boot_device,
+                      kernel_filename, kernel_cmdline, initrd_filename,
+                      hwdefs[machine].machine_id);
+}
+
+/* SPARCstation 5 hardware initialisation */
+static void ss5_init(int ram_size, int vga_ram_size, int boot_device,
+                       DisplayState *ds, const char **fd_filename, int snapshot,
+                       const char *kernel_filename, const char *kernel_cmdline,
+                       const char *initrd_filename, const char *cpu_model)
+{
+    if (cpu_model == NULL)
+        cpu_model = "Fujitsu MB86904";
+    sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
+                      kernel_cmdline, initrd_filename, cpu_model,
+                      0);
 }
-QEMUMachine sun4m_machine = {
-    "sun4m",
-    "Sun4m platform",
-    sun4m_init,
+QEMUMachine ss5_machine = {
+    "SS-5",
+    "Sun4m platform, SPARCstation 5",
+    ss5_init,
 };
@@ -6690,7 +6690,7 @@ void register_machines(void)
 #ifdef TARGET_SPARC64
     qemu_register_machine(&sun4u_machine);
 #else
-    qemu_register_machine(&sun4m_machine);
+    qemu_register_machine(&ss5_machine);
 #endif
 #elif defined(TARGET_ARM)
     qemu_register_machine(&integratorcp_machine);
@@ -1143,7 +1143,7 @@ extern CPUReadMemoryFunc *PPC_io_read[];
 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
 /* sun4m.c */
-extern QEMUMachine sun4m_machine;
+extern QEMUMachine ss5_machine;
 void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
 /* iommu.c */
@@ -1169,7 +1169,7 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
 	       unsigned long vram_offset, int vram_size, int width, int height);
 /* slavio_intctl.c */
-void *slavio_intctl_init();
+void *slavio_intctl_init(uint32_t addr, uint32_t addrg);
 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
 void slavio_pic_info(void *opaque);
 void slavio_irq_info(void *opaque);