gwj / at91sam9263 · Commits

Commit 3608160206ed55c35be916df0f5d43dccc183513

Authored by j_mayer
1 parent 3b46e624

Coding style fixes in PowerPC related code (no functional change): 

- avoid useless blanks at EOL.
- avoid tabs.
- fix wrapping lines on 80 chars terminals.
- add missing ';' at macros EOL to avoid confusing auto-identers.
- fix identation.
- Remove historical macros in micro-ops (PARAM, SPARAM, PPC_OP, regs)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3178 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 13 changed files with 274 additions and 267 deletions
hw/ppc405_uc.c
  View file @3608160
... ... @@ -924,7 +924,8 @@ enum {
924 924 SDRAM0_CFGDATA = 0x011,
925 925 };
926 926  
927   -static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size)
  927 +static uint32_t sdram_bcr (target_phys_addr_t ram_base,
  928 + target_phys_addr_t ram_size)
928 929 {
929 930 uint32_t bcr;
930 931  
... ... @@ -1217,9 +1218,11 @@ void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1217 1218 sdram->irq = irq;
1218 1219 sdram->nbanks = nbanks;
1219 1220 memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
1220   - memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t));
  1221 + memcpy(sdram->ram_bases, ram_bases,
  1222 + nbanks * sizeof(target_phys_addr_t));
1221 1223 memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
1222   - memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t));
  1224 + memcpy(sdram->ram_sizes, ram_sizes,
  1225 + nbanks * sizeof(target_phys_addr_t));
1223 1226 sdram_reset(sdram);
1224 1227 qemu_register_reset(&sdram_reset, sdram);
1225 1228 ppc_dcr_register(env, SDRAM0_CFGADDR,
... ... @@ -2212,7 +2215,6 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
2212 2215 }
2213 2216 mask = mask >> 1;
2214 2217 }
2215   -
2216 2218 }
2217 2219  
2218 2220 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
... ... @@ -2228,7 +2230,6 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
2228 2230 qemu_irq_lower(gpt->irqs[i]);
2229 2231 mask = mask >> 1;
2230 2232 }
2231   -
2232 2233 }
2233 2234  
2234 2235 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
... ...
hw/ppc_chrp.c
  View file @3608160
... ... @@ -46,22 +46,26 @@ static int macio_nvram_mem_index = -1;
46 46  
47 47 /* DBDMA: currently no op - should suffice right now */
48 48  
49   -static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
  49 +static void dbdma_writeb (void *opaque,
  50 + target_phys_addr_t addr, uint32_t value)
50 51 {
51 52 printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
52 53 }
53 54  
54   -static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
  55 +static void dbdma_writew (void *opaque,
  56 + target_phys_addr_t addr, uint32_t value)
55 57 {
56 58 }
57 59  
58   -static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
  60 +static void dbdma_writel (void *opaque,
  61 + target_phys_addr_t addr, uint32_t value)
59 62 {
60 63 }
61 64  
62 65 static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
63 66 {
64 67 printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
  68 +
65 69 return 0;
66 70 }
67 71  
... ... @@ -92,7 +96,8 @@ typedef struct MacIONVRAMState {
92 96 uint8_t data[0x2000];
93 97 } MacIONVRAMState;
94 98  
95   -static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
  99 +static void macio_nvram_writeb (void *opaque,
  100 + target_phys_addr_t addr, uint32_t value)
96 101 {
97 102 MacIONVRAMState *s = opaque;
98 103 addr = (addr >> 4) & 0x1fff;
... ... @@ -108,6 +113,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
108 113 addr = (addr >> 4) & 0x1fff;
109 114 value = s->data[addr];
110 115 // printf("macio_nvram_readb %04x = %02x\n", addr, value);
  116 +
111 117 return value;
112 118 }
113 119  
... ... @@ -123,7 +129,7 @@ static CPUReadMemoryFunc *macio_nvram_read[] = {
123 129 &macio_nvram_readb,
124 130 };
125 131  
126   -static MacIONVRAMState *macio_nvram_init(void)
  132 +static MacIONVRAMState *macio_nvram_init (void)
127 133 {
128 134 MacIONVRAMState *s;
129 135 s = qemu_mallocz(sizeof(MacIONVRAMState));
... ... @@ -131,11 +137,12 @@ static MacIONVRAMState *macio_nvram_init(void)
131 137 return NULL;
132 138 macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
133 139 macio_nvram_write, s);
  140 +
134 141 return s;
135 142 }
136 143  
137   -static void macio_map(PCIDevice *pci_dev, int region_num,
138   - uint32_t addr, uint32_t size, int type)
  144 +static void macio_map (PCIDevice *pci_dev, int region_num,
  145 + uint32_t addr, uint32_t size, int type)
139 146 {
140 147 if (heathrow_pic_mem_index >= 0) {
141 148 cpu_register_physical_memory(addr + 0x00000, 0x1000,
... ... @@ -152,10 +159,11 @@ static void macio_map(PCIDevice *pci_dev, int region_num,
152 159 openpic_mem_index);
153 160 }
154 161 if (macio_nvram_mem_index >= 0)
155   - cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
  162 + cpu_register_physical_memory(addr + 0x60000, 0x20000,
  163 + macio_nvram_mem_index);
156 164 }
157 165  
158   -static void macio_init(PCIBus *bus, int device_id)
  166 +static void macio_init (PCIBus *bus, int device_id)
159 167 {
160 168 PCIDevice *d;
161 169  
... ... @@ -204,7 +212,8 @@ static CPUReadMemoryFunc *unin_read[] = {
204 212  
205 213 /* temporary frame buffer OSI calls for the video.x driver. The right
206 214 solution is to modify the driver to use VGA PCI I/Os */
207   -static int vga_osi_call(CPUState *env)
  215 +/* XXX: to be removed. This is no way related to emulation */
  216 +static int vga_osi_call (CPUState *env)
208 217 {
209 218 static int vga_vbl_enabled;
210 219 int linesize;
... ... @@ -264,10 +273,11 @@ static int vga_osi_call(CPUState *env)
264 273 fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
265 274 break;
266 275 }
  276 +
267 277 return 1; /* osi_call handled */
268 278 }
269 279  
270   -static uint8_t nvram_chksum(const uint8_t *buf, int n)
  280 +static uint8_t nvram_chksum (const uint8_t *buf, int n)
271 281 {
272 282 int sum, i;
273 283 sum = 0;
... ... @@ -277,7 +287,7 @@ static uint8_t nvram_chksum(const uint8_t *buf, int n)
277 287 }
278 288  
279 289 /* set a free Mac OS NVRAM partition */
280   -void pmac_format_nvram_partition(uint8_t *buf, int len)
  290 +void pmac_format_nvram_partition (uint8_t *buf, int len)
281 291 {
282 292 char partition_name[12] = "wwwwwwwwwwww";
283 293  
... ... @@ -503,8 +513,7 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
503 513 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
504 514 break;
505 515 default:
506   - cpu_abort(env,
507   - "Only bus model not supported on mac99 machine\n");
  516 + cpu_abort(env, "Bus model not supported on mac99 machine\n");
508 517 exit(1);
509 518 }
510 519 }
... ...
hw/ppc_prep.c
  View file @3608160
... ... @@ -76,7 +76,7 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
76 76 int speaker_data_on;
77 77 int dummy_refresh_clock;
78 78  
79   -static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
  79 +static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
80 80 {
81 81 #if 0
82 82 speaker_data_on = (val >> 1) & 1;
... ... @@ -110,7 +110,7 @@ static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
110 110  
111 111 if (addr == 0xBFFFFFF0)
112 112 retval = pic_intack_read(isa_pic);
113   - // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
  113 + // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
114 114  
115 115 return retval;
116 116 }
... ... @@ -177,12 +177,14 @@ static struct {
177 177 /* Error diagnostic */
178 178 } XCSR;
179 179  
180   -static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
  180 +static void PPC_XCSR_writeb (void *opaque,
  181 + target_phys_addr_t addr, uint32_t value)
181 182 {
182 183 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
183 184 }
184 185  
185   -static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
  186 +static void PPC_XCSR_writew (void *opaque,
  187 + target_phys_addr_t addr, uint32_t value)
186 188 {
187 189 #ifdef TARGET_WORDS_BIGENDIAN
188 190 value = bswap16(value);
... ... @@ -190,7 +192,8 @@ static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t val
190 192 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
191 193 }
192 194  
193   -static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
  195 +static void PPC_XCSR_writel (void *opaque,
  196 + target_phys_addr_t addr, uint32_t value)
194 197 {
195 198 #ifdef TARGET_WORDS_BIGENDIAN
196 199 value = bswap32(value);
... ... @@ -664,7 +667,8 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
664 667 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
665 668 /* PowerPC control and status register group */
666 669 #if 0
667   - PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
  670 + PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
  671 + NULL);
668 672 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
669 673 #endif
670 674  
... ...
target-ppc/cpu.h
  View file @3608160
... ... @@ -822,18 +822,18 @@ struct mmu_ctx_t {
822 822 };
823 823  
824 824 /*****************************************************************************/
825   -CPUPPCState *cpu_ppc_init(void);
826   -int cpu_ppc_exec(CPUPPCState *s);
827   -void cpu_ppc_close(CPUPPCState *s);
  825 +CPUPPCState *cpu_ppc_init (void);
  826 +int cpu_ppc_exec (CPUPPCState *s);
  827 +void cpu_ppc_close (CPUPPCState *s);
828 828 /* you can call this signal handler from your SIGBUS and SIGSEGV
829 829 signal handlers to inform the virtual CPU of exceptions. non zero
830 830 is returned if the signal was handled by the virtual CPU. */
831   -int cpu_ppc_signal_handler(int host_signum, void *pinfo,
832   - void *puc);
  831 +int cpu_ppc_signal_handler (int host_signum, void *pinfo,
  832 + void *puc);
833 833  
834 834 void do_interrupt (CPUPPCState *env);
835 835 void ppc_hw_interrupt (CPUPPCState *env);
836   -void cpu_loop_exit(void);
  836 +void cpu_loop_exit (void);
837 837  
838 838 void dump_stack (CPUPPCState *env);
839 839  
... ... @@ -891,7 +891,7 @@ void store_40x_sler (CPUPPCState *env, uint32_t val);
891 891 void store_booke_tcr (CPUPPCState *env, target_ulong val);
892 892 void store_booke_tsr (CPUPPCState *env, target_ulong val);
893 893 void ppc_tlb_invalidate_all (CPUPPCState *env);
894   -int ppcemb_tlb_search (CPUPPCState *env, target_ulong address);
  894 +int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
895 895 #endif
896 896 #endif
897 897  
... ... @@ -915,12 +915,12 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
915 915 #define XER_OV 30
916 916 #define XER_CA 29
917 917 #define XER_CMP 8
918   -#define XER_BC 0
  918 +#define XER_BC 0
919 919 #define xer_so env->xer[4]
920 920 #define xer_ov env->xer[6]
921 921 #define xer_ca env->xer[2]
922 922 #define xer_cmp env->xer[1]
923   -#define xer_bc env->xer[0]
  923 +#define xer_bc env->xer[0]
924 924  
925 925 /* SPR definitions */
926 926 #define SPR_MQ (0x000)
... ...
target-ppc/exec.h
  View file @3608160
... ... @@ -58,10 +58,6 @@ register unsigned long T2 asm(AREG3);
58 58 #define T1_avr (env->t1_avr)
59 59 #define T2_avr (env->t2_avr)
60 60  
61   -/* XXX: to clean: remove this mess */
62   -#define PARAM(n) ((uint32_t)PARAM##n)
63   -#define SPARAM(n) ((int32_t)PARAM##n)
64   -
65 61 #define FT0 (env->ft0)
66 62 #define FT1 (env->ft1)
67 63 #define FT2 (env->ft2)
... ... @@ -111,18 +107,19 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
111 107 target_ulong pte0, target_ulong pte1);
112 108 void ppc4xx_tlb_invalidate_all (CPUState *env);
113 109  
114   -static inline void env_to_regs(void)
  110 +static inline void env_to_regs (void)
115 111 {
116 112 }
117 113  
118   -static inline void regs_to_env(void)
  114 +static inline void regs_to_env (void)
119 115 {
120 116 }
121 117  
122 118 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
123 119 int is_user, int is_softmmu);
124 120  
125   -static inline int cpu_halted(CPUState *env) {
  121 +static inline int cpu_halted (CPUState *env)
  122 +{
126 123 if (!env->halted)
127 124 return 0;
128 125 if (env->msr[MSR_EE] && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
... ...
target-ppc/helper.c
  View file @3608160
... ... @@ -64,6 +64,7 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64 64 {
65 65 return addr;
66 66 }
  67 +
67 68 #else
68 69 /* Common routines used by software and hardware TLBs emulation */
69 70 static inline int pte_is_valid (target_ulong pte0)
... ... @@ -635,7 +636,8 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
635 636 /* Generic TLB check function for embedded PowerPC implementations */
636 637 static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
637 638 target_phys_addr_t *raddrp,
638   - target_ulong address, int i)
  639 + target_ulong address,
  640 + uint32_t pid, int ext, int i)
639 641 {
640 642 target_ulong mask;
641 643  
... ... @@ -649,22 +651,25 @@ static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
649 651 if (loglevel != 0) {
650 652 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
651 653 ADDRX " " ADDRX " %d\n",
652   - __func__, i, address, (int)env->spr[SPR_40x_PID],
653   - tlb->EPN, mask, (int)tlb->PID);
  654 + __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
654 655 }
655 656 /* Check PID */
656   - if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
  657 + if (tlb->PID != 0 && tlb->PID != pid)
657 658 return -1;
658 659 /* Check effective address */
659 660 if ((address & mask) != tlb->EPN)
660 661 return -1;
661 662 *raddrp = (tlb->RPN & mask) | (address & ~mask);
  663 + if (ext) {
  664 + /* Extend the physical address to 36 bits */
  665 + *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
  666 + }
662 667  
663 668 return 0;
664 669 }
665 670  
666 671 /* Generic TLB search function for PowerPC embedded implementations */
667   -int ppcemb_tlb_search (CPUState *env, target_ulong address)
  672 +int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
668 673 {
669 674 ppcemb_tlb_t *tlb;
670 675 target_phys_addr_t raddr;
... ... @@ -674,7 +679,7 @@ int ppcemb_tlb_search (CPUState *env, target_ulong address)
674 679 ret = -1;
675 680 for (i = 0; i < 64; i++) {
676 681 tlb = &env->tlb[i].tlbe;
677   - if (ppcemb_tlb_check(env, tlb, &raddr, address, i) == 0) {
  682 + if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
678 683 ret = i;
679 684 break;
680 685 }
... ... @@ -703,7 +708,7 @@ void ppc4xx_tlb_invalidate_all (CPUState *env)
703 708 tlb_flush(env, 1);
704 709 }
705 710  
706   -int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
  711 +int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
707 712 target_ulong address, int rw, int access_type)
708 713 {
709 714 ppcemb_tlb_t *tlb;
... ... @@ -714,7 +719,8 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
714 719 raddr = -1;
715 720 for (i = 0; i < env->nb_tlb; i++) {
716 721 tlb = &env->tlb[i].tlbe;
717   - if (ppcemb_tlb_check(env, tlb, &raddr, address, i) < 0)
  722 + if (ppcemb_tlb_check(env, tlb, &raddr, address,
  723 + env->spr[SPR_40x_PID], 0, i) < 0)
718 724 continue;
719 725 zsel = (tlb->attr >> 4) & 0xF;
720 726 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
... ... @@ -890,7 +896,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
890 896 break;
891 897 case PPC_FLAGS_MMU_SOFT_4xx:
892 898 case PPC_FLAGS_MMU_403:
893   - ret = mmu4xx_get_physical_address(env, ctx, eaddr,
  899 + ret = mmu40x_get_physical_address(env, ctx, eaddr,
894 900 rw, access_type);
895 901 break;
896 902 case PPC_FLAGS_MMU_601:
... ... @@ -1536,7 +1542,7 @@ void ppc_hw_interrupt (CPUState *env)
1536 1542 env->exception_index = -1;
1537 1543 }
1538 1544 #else /* defined (CONFIG_USER_ONLY) */
1539   -static void dump_syscall(CPUState *env)
  1545 +static void dump_syscall (CPUState *env)
1540 1546 {
1541 1547 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1542 1548 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
... ...
target-ppc/op.c
  View file @3608160
... ... @@ -24,16 +24,6 @@
24 24 #include "exec.h"
25 25 #include "op_helper.h"
26 26  
27   -/* XXX: this is to be suppressed */
28   -#define regs (env)
29   -
30   -#define FT0 (env->ft0)
31   -#define FT1 (env->ft1)
32   -#define FT2 (env->ft2)
33   -
34   -/* XXX: this is to be suppressed... */
35   -#define PPC_OP(name) void OPPROTO glue(op_, name)(void)
36   -
37 27 #define REG 0
38 28 #include "op_template.h"
39 29  
... ... @@ -139,16 +129,16 @@ void OPPROTO op_print_mem_EA (void)
139 129  
140 130 /* PowerPC state maintenance operations */
141 131 /* set_Rc0 */
142   -PPC_OP(set_Rc0)
  132 +void OPPROTO op_set_Rc0 (void)
143 133 {
144 134 env->crf[0] = T0 | xer_ov;
145 135 RETURN();
146 136 }
147 137  
148 138 /* Set Rc1 (for floating point arithmetic) */
149   -PPC_OP(set_Rc1)
  139 +void OPPROTO op_set_Rc1 (void)
150 140 {
151   - env->crf[1] = regs->fpscr[7];
  141 + env->crf[1] = env->fpscr[7];
152 142 RETURN();
153 143 }
154 144  
... ... @@ -159,7 +149,7 @@ void OPPROTO op_reset_T0 (void)
159 149 RETURN();
160 150 }
161 151  
162   -PPC_OP(set_T0)
  152 +void OPPROTO op_set_T0 (void)
163 153 {
164 154 T0 = (uint32_t)PARAM1;
165 155 RETURN();
... ... @@ -173,7 +163,7 @@ void OPPROTO op_set_T0_64 (void)
173 163 }
174 164 #endif
175 165  
176   -PPC_OP(set_T1)
  166 +void OPPROTO op_set_T1 (void)
177 167 {
178 168 T1 = (uint32_t)PARAM1;
179 169 RETURN();
... ... @@ -188,9 +178,9 @@ void OPPROTO op_set_T1_64 (void)
188 178 #endif
189 179  
190 180 #if 0 // unused
191   -PPC_OP(set_T2)
  181 +void OPPROTO op_set_T2 (void)
192 182 {
193   - T2 = PARAM(1);
  183 + T2 = PARAM1;
194 184 RETURN();
195 185 }
196 186 #endif
... ... @@ -208,12 +198,12 @@ void OPPROTO op_move_T2_T0 (void)
208 198 }
209 199  
210 200 /* Generate exceptions */
211   -PPC_OP(raise_exception_err)
  201 +void OPPROTO op_raise_exception_err (void)
212 202 {
213   - do_raise_exception_err(PARAM(1), PARAM(2));
  203 + do_raise_exception_err(PARAM1, PARAM2);
214 204 }
215 205  
216   -PPC_OP(update_nip)
  206 +void OPPROTO op_update_nip (void)
217 207 {
218 208 env->nip = (uint32_t)PARAM1;
219 209 RETURN();
... ... @@ -227,26 +217,26 @@ void OPPROTO op_update_nip_64 (void)
227 217 }
228 218 #endif
229 219  
230   -PPC_OP(debug)
  220 +void OPPROTO op_debug (void)
231 221 {
232 222 do_raise_exception(EXCP_DEBUG);
233 223 }
234 224  
235   -PPC_OP(exit_tb)
  225 +void OPPROTO op_exit_tb (void)
236 226 {
237 227 EXIT_TB();
238 228 }
239 229  
240 230 /* Load/store special registers */
241   -PPC_OP(load_cr)
  231 +void OPPROTO op_load_cr (void)
242 232 {
243 233 do_load_cr();
244 234 RETURN();
245 235 }
246 236  
247   -PPC_OP(store_cr)
  237 +void OPPROTO op_store_cr (void)
248 238 {
249   - do_store_cr(PARAM(1));
  239 + do_store_cr(PARAM1);
250 240 RETURN();
251 241 }
252 242  
... ... @@ -262,26 +252,26 @@ void OPPROTO op_store_cro (void)
262 252 RETURN();
263 253 }
264 254  
265   -PPC_OP(load_xer_cr)
  255 +void OPPROTO op_load_xer_cr (void)
266 256 {
267 257 T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1);
268 258 RETURN();
269 259 }
270 260  
271   -PPC_OP(clear_xer_ov)
  261 +void OPPROTO op_clear_xer_ov (void)
272 262 {
273 263 xer_so = 0;
274 264 xer_ov = 0;
275 265 RETURN();
276 266 }
277 267  
278   -PPC_OP(clear_xer_ca)
  268 +void OPPROTO op_clear_xer_ca (void)
279 269 {
280 270 xer_ca = 0;
281 271 RETURN();
282 272 }
283 273  
284   -PPC_OP(load_xer_bc)
  274 +void OPPROTO op_load_xer_bc (void)
285 275 {
286 276 T1 = xer_bc;
287 277 RETURN();
... ... @@ -293,13 +283,13 @@ void OPPROTO op_store_xer_bc (void)
293 283 RETURN();
294 284 }
295 285  
296   -PPC_OP(load_xer)
  286 +void OPPROTO op_load_xer (void)
297 287 {
298 288 do_load_xer();
299 289 RETURN();
300 290 }
301 291  
302   -PPC_OP(store_xer)
  292 +void OPPROTO op_store_xer (void)
303 293 {
304 294 do_store_xer();
305 295 RETURN();
... ... @@ -307,25 +297,25 @@ PPC_OP(store_xer)
307 297  
308 298 #if !defined(CONFIG_USER_ONLY)
309 299 /* Segment registers load and store */
310   -PPC_OP(load_sr)
  300 +void OPPROTO op_load_sr (void)
311 301 {
312   - T0 = regs->sr[T1];
  302 + T0 = env->sr[T1];
313 303 RETURN();
314 304 }
315 305  
316   -PPC_OP(store_sr)
  306 +void OPPROTO op_store_sr (void)
317 307 {
318 308 do_store_sr(env, T1, T0);
319 309 RETURN();
320 310 }
321 311  
322   -PPC_OP(load_sdr1)
  312 +void OPPROTO op_load_sdr1 (void)
323 313 {
324   - T0 = regs->sdr1;
  314 + T0 = env->sdr1;
325 315 RETURN();
326 316 }
327 317  
328   -PPC_OP(store_sdr1)
  318 +void OPPROTO op_store_sdr1 (void)
329 319 {
330 320 do_store_sdr1(env, T0);
331 321 RETURN();
... ... @@ -345,13 +335,13 @@ void OPPROTO op_store_asr (void)
345 335 }
346 336 #endif
347 337  
348   -PPC_OP(load_msr)
  338 +void OPPROTO op_load_msr (void)
349 339 {
350 340 T0 = do_load_msr(env);
351 341 RETURN();
352 342 }
353 343  
354   -PPC_OP(store_msr)
  344 +void OPPROTO op_store_msr (void)
355 345 {
356 346 do_store_msr(env, T0);
357 347 RETURN();
... ... @@ -397,70 +387,70 @@ void OPPROTO op_mask_spr (void)
397 387 RETURN();
398 388 }
399 389  
400   -PPC_OP(load_lr)
  390 +void OPPROTO op_load_lr (void)
401 391 {
402   - T0 = regs->lr;
  392 + T0 = env->lr;
403 393 RETURN();
404 394 }
405 395  
406   -PPC_OP(store_lr)
  396 +void OPPROTO op_store_lr (void)
407 397 {
408   - regs->lr = T0;
  398 + env->lr = T0;
409 399 RETURN();
410 400 }
411 401  
412   -PPC_OP(load_ctr)
  402 +void OPPROTO op_load_ctr (void)
413 403 {
414   - T0 = regs->ctr;
  404 + T0 = env->ctr;
415 405 RETURN();
416 406 }
417 407  
418   -PPC_OP(store_ctr)
  408 +void OPPROTO op_store_ctr (void)
419 409 {
420   - regs->ctr = T0;
  410 + env->ctr = T0;
421 411 RETURN();
422 412 }
423 413  
424   -PPC_OP(load_tbl)
  414 +void OPPROTO op_load_tbl (void)
425 415 {
426   - T0 = cpu_ppc_load_tbl(regs);
  416 + T0 = cpu_ppc_load_tbl(env);
427 417 RETURN();
428 418 }
429 419  
430   -PPC_OP(load_tbu)
  420 +void OPPROTO op_load_tbu (void)
431 421 {
432   - T0 = cpu_ppc_load_tbu(regs);
  422 + T0 = cpu_ppc_load_tbu(env);
433 423 RETURN();
434 424 }
435 425  
436 426 #if !defined(CONFIG_USER_ONLY)
437   -PPC_OP(store_tbl)
  427 +void OPPROTO op_store_tbl (void)
438 428 {
439   - cpu_ppc_store_tbl(regs, T0);
  429 + cpu_ppc_store_tbl(env, T0);
440 430 RETURN();
441 431 }
442 432  
443   -PPC_OP(store_tbu)
  433 +void OPPROTO op_store_tbu (void)
444 434 {
445   - cpu_ppc_store_tbu(regs, T0);
  435 + cpu_ppc_store_tbu(env, T0);
446 436 RETURN();
447 437 }
448 438  
449   -PPC_OP(load_decr)
  439 +void OPPROTO op_load_decr (void)
450 440 {
451   - T0 = cpu_ppc_load_decr(regs);
  441 + T0 = cpu_ppc_load_decr(env);
452 442 RETURN();
453 443 }
454 444  
455   -PPC_OP(store_decr)
  445 +void OPPROTO op_store_decr (void)
456 446 {
457   - cpu_ppc_store_decr(regs, T0);
  447 + cpu_ppc_store_decr(env, T0);
458 448 RETURN();
459 449 }
460 450  
461   -PPC_OP(load_ibat)
  451 +void OPPROTO op_load_ibat (void)
462 452 {
463   - T0 = regs->IBAT[PARAM(1)][PARAM(2)];
  453 + T0 = env->IBAT[PARAM1][PARAM2];
464 454 RETURN();
465 455 }
466 456  
... ... @@ -480,9 +470,9 @@ void OPPROTO op_store_ibatl (void)
480 470 RETURN();
481 471 }
482 472  
483   -PPC_OP(load_dbat)
  473 +void OPPROTO op_load_dbat (void)
484 474 {
485   - T0 = regs->DBAT[PARAM(1)][PARAM(2)];
  475 + T0 = env->DBAT[PARAM1][PARAM2];
486 476 RETURN();
487 477 }
488 478  
... ... @@ -504,85 +494,85 @@ void OPPROTO op_store_dbatl (void)
504 494 #endif /* !defined(CONFIG_USER_ONLY) */
505 495  
506 496 /* FPSCR */
507   -PPC_OP(load_fpscr)
  497 +void OPPROTO op_load_fpscr (void)
508 498 {
509 499 do_load_fpscr();
510 500 RETURN();
511 501 }
512 502  
513   -PPC_OP(store_fpscr)
  503 +void OPPROTO op_store_fpscr (void)
514 504 {
515 505 do_store_fpscr(PARAM1);
516 506 RETURN();
517 507 }
518 508  
519   -PPC_OP(reset_scrfx)
  509 +void OPPROTO op_reset_scrfx (void)
520 510 {
521   - regs->fpscr[7] &= ~0x8;
  511 + env->fpscr[7] &= ~0x8;
522 512 RETURN();
523 513 }
524 514  
525 515 /* crf operations */
526   -PPC_OP(getbit_T0)
  516 +void OPPROTO op_getbit_T0 (void)
527 517 {
528   - T0 = (T0 >> PARAM(1)) & 1;
  518 + T0 = (T0 >> PARAM1) & 1;
529 519 RETURN();
530 520 }
531 521  
532   -PPC_OP(getbit_T1)
  522 +void OPPROTO op_getbit_T1 (void)
533 523 {
534   - T1 = (T1 >> PARAM(1)) & 1;
  524 + T1 = (T1 >> PARAM1) & 1;
535 525 RETURN();
536 526 }
537 527  
538   -PPC_OP(setcrfbit)
  528 +void OPPROTO op_setcrfbit (void)
539 529 {
540   - T1 = (T1 & PARAM(1)) | (T0 << PARAM(2));
  530 + T1 = (T1 & PARAM1) | (T0 << PARAM2);
541 531 RETURN();
542 532 }
543 533  
544 534 /* Branch */
545   -#define EIP regs->nip
  535 +#define EIP env->nip
546 536  
547   -PPC_OP(setlr)
  537 +void OPPROTO op_setlr (void)
548 538 {
549   - regs->lr = (uint32_t)PARAM1;
  539 + env->lr = (uint32_t)PARAM1;
550 540 RETURN();
551 541 }
552 542  
553 543 #if defined (TARGET_PPC64)
554 544 void OPPROTO op_setlr_64 (void)
555 545 {
556   - regs->lr = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
  546 + env->lr = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
557 547 RETURN();
558 548 }
559 549 #endif
560 550  
561   -PPC_OP(goto_tb0)
  551 +void OPPROTO op_goto_tb0 (void)
562 552 {
563 553 GOTO_TB(op_goto_tb0, PARAM1, 0);
564 554 }
565 555  
566   -PPC_OP(goto_tb1)
  556 +void OPPROTO op_goto_tb1 (void)
567 557 {
568 558 GOTO_TB(op_goto_tb1, PARAM1, 1);
569 559 }
570 560  
571 561 void OPPROTO op_b_T1 (void)
572 562 {
573   - regs->nip = (uint32_t)(T1 & ~3);
  563 + env->nip = (uint32_t)(T1 & ~3);
574 564 RETURN();
575 565 }
576 566  
577 567 #if defined (TARGET_PPC64)
578 568 void OPPROTO op_b_T1_64 (void)
579 569 {
580   - regs->nip = (uint64_t)(T1 & ~3);
  570 + env->nip = (uint64_t)(T1 & ~3);
581 571 RETURN();
582 572 }
583 573 #endif
584 574  
585   -PPC_OP(jz_T0)
  575 +void OPPROTO op_jz_T0 (void)
586 576 {
587 577 if (!T0)
588 578 GOTO_LABEL_PARAM(1);
... ... @@ -592,9 +582,9 @@ PPC_OP(jz_T0)
592 582 void OPPROTO op_btest_T1 (void)
593 583 {
594 584 if (T0) {
595   - regs->nip = (uint32_t)(T1 & ~3);
  585 + env->nip = (uint32_t)(T1 & ~3);
596 586 } else {
597   - regs->nip = (uint32_t)PARAM1;
  587 + env->nip = (uint32_t)PARAM1;
598 588 }
599 589 RETURN();
600 590 }
... ... @@ -603,133 +593,133 @@ void OPPROTO op_btest_T1 (void)
603 593 void OPPROTO op_btest_T1_64 (void)
604 594 {
605 595 if (T0) {
606   - regs->nip = (uint64_t)(T1 & ~3);
  596 + env->nip = (uint64_t)(T1 & ~3);
607 597 } else {
608   - regs->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
  598 + env->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
609 599 }
610 600 RETURN();
611 601 }
612 602 #endif
613 603  
614   -PPC_OP(movl_T1_ctr)
  604 +void OPPROTO op_movl_T1_ctr (void)
615 605 {
616   - T1 = regs->ctr;
  606 + T1 = env->ctr;
617 607 RETURN();
618 608 }
619 609  
620   -PPC_OP(movl_T1_lr)
  610 +void OPPROTO op_movl_T1_lr (void)
621 611 {
622   - T1 = regs->lr;
  612 + T1 = env->lr;
623 613 RETURN();
624 614 }
625 615  
626 616 /* tests with result in T0 */
627 617 void OPPROTO op_test_ctr (void)
628 618 {
629   - T0 = (uint32_t)regs->ctr;
  619 + T0 = (uint32_t)env->ctr;
630 620 RETURN();
631 621 }
632 622  
633 623 #if defined(TARGET_PPC64)
634 624 void OPPROTO op_test_ctr_64 (void)
635 625 {
636   - T0 = (uint64_t)regs->ctr;
  626 + T0 = (uint64_t)env->ctr;
637 627 RETURN();
638 628 }
639 629 #endif
640 630  
641 631 void OPPROTO op_test_ctr_true (void)
642 632 {
643   - T0 = ((uint32_t)regs->ctr != 0 && (T0 & PARAM1) != 0);
  633 + T0 = ((uint32_t)env->ctr != 0 && (T0 & PARAM1) != 0);
644 634 RETURN();
645 635 }
646 636  
647 637 #if defined(TARGET_PPC64)
648 638 void OPPROTO op_test_ctr_true_64 (void)
649 639 {
650   - T0 = ((uint64_t)regs->ctr != 0 && (T0 & PARAM1) != 0);
  640 + T0 = ((uint64_t)env->ctr != 0 && (T0 & PARAM1) != 0);
651 641 RETURN();
652 642 }
653 643 #endif
654 644  
655 645 void OPPROTO op_test_ctr_false (void)
656 646 {
657   - T0 = ((uint32_t)regs->ctr != 0 && (T0 & PARAM1) == 0);
  647 + T0 = ((uint32_t)env->ctr != 0 && (T0 & PARAM1) == 0);
658 648 RETURN();
659 649 }
660 650  
661 651 #if defined(TARGET_PPC64)
662 652 void OPPROTO op_test_ctr_false_64 (void)
663 653 {
664   - T0 = ((uint64_t)regs->ctr != 0 && (T0 & PARAM1) == 0);
  654 + T0 = ((uint64_t)env->ctr != 0 && (T0 & PARAM1) == 0);
665 655 RETURN();
666 656 }
667 657 #endif
668 658  
669 659 void OPPROTO op_test_ctrz (void)
670 660 {
671   - T0 = ((uint32_t)regs->ctr == 0);
  661 + T0 = ((uint32_t)env->ctr == 0);
672 662 RETURN();
673 663 }
674 664  
675 665 #if defined(TARGET_PPC64)
676 666 void OPPROTO op_test_ctrz_64 (void)
677 667 {
678   - T0 = ((uint64_t)regs->ctr == 0);
  668 + T0 = ((uint64_t)env->ctr == 0);
679 669 RETURN();
680 670 }
681 671 #endif
682 672  
683 673 void OPPROTO op_test_ctrz_true (void)
684 674 {
685   - T0 = ((uint32_t)regs->ctr == 0 && (T0 & PARAM1) != 0);
  675 + T0 = ((uint32_t)env->ctr == 0 && (T0 & PARAM1) != 0);
686 676 RETURN();
687 677 }
688 678  
689 679 #if defined(TARGET_PPC64)
690 680 void OPPROTO op_test_ctrz_true_64 (void)
691 681 {
692   - T0 = ((uint64_t)regs->ctr == 0 && (T0 & PARAM1) != 0);
  682 + T0 = ((uint64_t)env->ctr == 0 && (T0 & PARAM1) != 0);
693 683 RETURN();
694 684 }
695 685 #endif
696 686  
697 687 void OPPROTO op_test_ctrz_false (void)
698 688 {
699   - T0 = ((uint32_t)regs->ctr == 0 && (T0 & PARAM1) == 0);
  689 + T0 = ((uint32_t)env->ctr == 0 && (T0 & PARAM1) == 0);
700 690 RETURN();
701 691 }
702 692  
703 693 #if defined(TARGET_PPC64)
704 694 void OPPROTO op_test_ctrz_false_64 (void)
705 695 {
706   - T0 = ((uint64_t)regs->ctr == 0 && (T0 & PARAM1) == 0);
  696 + T0 = ((uint64_t)env->ctr == 0 && (T0 & PARAM1) == 0);
707 697 RETURN();
708 698 }
709 699 #endif
710 700  
711   -PPC_OP(test_true)
  701 +void OPPROTO op_test_true (void)
712 702 {
713   - T0 = (T0 & PARAM(1));
  703 + T0 = (T0 & PARAM1);
714 704 RETURN();
715 705 }
716 706  
717   -PPC_OP(test_false)
  707 +void OPPROTO op_test_false (void)
718 708 {
719   - T0 = ((T0 & PARAM(1)) == 0);
  709 + T0 = ((T0 & PARAM1) == 0);
720 710 RETURN();
721 711 }
722 712  
723 713 /* CTR maintenance */
724   -PPC_OP(dec_ctr)
  714 +void OPPROTO op_dec_ctr (void)
725 715 {
726   - regs->ctr--;
  716 + env->ctr--;
727 717 RETURN();
728 718 }
729 719  
730 720 /*** Integer arithmetic ***/
731 721 /* add */
732   -PPC_OP(add)
  722 +void OPPROTO op_add (void)
733 723 {
734 724 T0 += T1;
735 725 RETURN();
... ... @@ -800,9 +790,9 @@ void OPPROTO op_adde_64 (void)
800 790 #endif
801 791  
802 792 /* add immediate */
803   -PPC_OP(addi)
  793 +void OPPROTO op_addi (void)
804 794 {
805   - T0 += (int32_t)PARAM(1);
  795 + T0 += (int32_t)PARAM1;
806 796 RETURN();
807 797 }
808 798  
... ... @@ -957,14 +947,14 @@ void OPPROTO op_mulhdu (void)
957 947 #endif
958 948  
959 949 /* multiply low immediate */
960   -PPC_OP(mulli)
  950 +void OPPROTO op_mulli (void)
961 951 {
962 952 T0 = ((int32_t)T0 * (int32_t)PARAM1);
963 953 RETURN();
964 954 }
965 955  
966 956 /* multiply low word */
967   -PPC_OP(mullw)
  957 +void OPPROTO op_mullw (void)
968 958 {
969 959 T0 = (int32_t)(T0 * T1);
970 960 RETURN();
... ... @@ -1026,7 +1016,7 @@ void OPPROTO op_nego_64 (void)
1026 1016 #endif
1027 1017  
1028 1018 /* subtract from */
1029   -PPC_OP(subf)
  1019 +void OPPROTO op_subf (void)
1030 1020 {
1031 1021 T0 = T1 - T0;
1032 1022 RETURN();
... ... @@ -1329,14 +1319,14 @@ void OPPROTO op_popcntb_64 (void)
1329 1319  
1330 1320 /*** Integer logical ***/
1331 1321 /* and */
1332   -PPC_OP(and)
  1322 +void OPPROTO op_and (void)
1333 1323 {
1334 1324 T0 &= T1;
1335 1325 RETURN();
1336 1326 }
1337 1327  
1338 1328 /* andc */
1339   -PPC_OP(andc)
  1329 +void OPPROTO op_andc (void)
1340 1330 {
1341 1331 T0 &= ~T1;
1342 1332 RETURN();
... ... @@ -1345,7 +1335,7 @@ PPC_OP(andc)
1345 1335 /* andi. */
1346 1336 void OPPROTO op_andi_T0 (void)
1347 1337 {
1348   - T0 &= PARAM(1);
  1338 + T0 &= PARAM1;
1349 1339 RETURN();
1350 1340 }
1351 1341  
... ... @@ -1371,7 +1361,7 @@ void OPPROTO op_cntlzd (void)
1371 1361 #endif
1372 1362  
1373 1363 /* eqv */
1374   -PPC_OP(eqv)
  1364 +void OPPROTO op_eqv (void)
1375 1365 {
1376 1366 T0 = ~(T0 ^ T1);
1377 1367 RETURN();
... ... @@ -1408,51 +1398,51 @@ void OPPROTO op_extsw (void)
1408 1398 #endif
1409 1399  
1410 1400 /* nand */
1411   -PPC_OP(nand)
  1401 +void OPPROTO op_nand (void)
1412 1402 {
1413 1403 T0 = ~(T0 & T1);
1414 1404 RETURN();
1415 1405 }
1416 1406  
1417 1407 /* nor */
1418   -PPC_OP(nor)
  1408 +void OPPROTO op_nor (void)
1419 1409 {
1420 1410 T0 = ~(T0 | T1);
1421 1411 RETURN();
1422 1412 }
1423 1413  
1424 1414 /* or */
1425   -PPC_OP(or)
  1415 +void OPPROTO op_or (void)
1426 1416 {
1427 1417 T0 |= T1;
1428 1418 RETURN();
1429 1419 }
1430 1420  
1431 1421 /* orc */
1432   -PPC_OP(orc)
  1422 +void OPPROTO op_orc (void)
1433 1423 {
1434 1424 T0 |= ~T1;
1435 1425 RETURN();
1436 1426 }
1437 1427  
1438 1428 /* ori */
1439   -PPC_OP(ori)
  1429 +void OPPROTO op_ori (void)
1440 1430 {
1441   - T0 |= PARAM(1);
  1431 + T0 |= PARAM1;
1442 1432 RETURN();
1443 1433 }
1444 1434  
1445 1435 /* xor */
1446   -PPC_OP(xor)
  1436 +void OPPROTO op_xor (void)
1447 1437 {
1448 1438 T0 ^= T1;
1449 1439 RETURN();
1450 1440 }
1451 1441  
1452 1442 /* xori */
1453   -PPC_OP(xori)
  1443 +void OPPROTO op_xori (void)
1454 1444 {
1455   - T0 ^= PARAM(1);
  1445 + T0 ^= PARAM1;
1456 1446 RETURN();
1457 1447 }
1458 1448  
... ... @@ -1630,56 +1620,56 @@ void OPPROTO op_srli_T1_64 (void)
1630 1620  
1631 1621 /*** Floating-Point arithmetic ***/
1632 1622 /* fadd - fadd. */
1633   -PPC_OP(fadd)
  1623 +void OPPROTO op_fadd (void)
1634 1624 {
1635 1625 FT0 = float64_add(FT0, FT1, &env->fp_status);
1636 1626 RETURN();
1637 1627 }
1638 1628  
1639 1629 /* fsub - fsub. */
1640   -PPC_OP(fsub)
  1630 +void OPPROTO op_fsub (void)
1641 1631 {
1642 1632 FT0 = float64_sub(FT0, FT1, &env->fp_status);
1643 1633 RETURN();
1644 1634 }
1645 1635  
1646 1636 /* fmul - fmul. */
1647   -PPC_OP(fmul)
  1637 +void OPPROTO op_fmul (void)
1648 1638 {
1649 1639 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1650 1640 RETURN();
1651 1641 }
1652 1642  
1653 1643 /* fdiv - fdiv. */
1654   -PPC_OP(fdiv)
  1644 +void OPPROTO op_fdiv (void)
1655 1645 {
1656 1646 FT0 = float64_div(FT0, FT1, &env->fp_status);
1657 1647 RETURN();
1658 1648 }
1659 1649  
1660 1650 /* fsqrt - fsqrt. */
1661   -PPC_OP(fsqrt)
  1651 +void OPPROTO op_fsqrt (void)
1662 1652 {
1663 1653 do_fsqrt();
1664 1654 RETURN();
1665 1655 }
1666 1656  
1667 1657 /* fres - fres. */
1668   -PPC_OP(fres)
  1658 +void OPPROTO op_fres (void)
1669 1659 {
1670 1660 do_fres();
1671 1661 RETURN();
1672 1662 }
1673 1663  
1674 1664 /* frsqrte - frsqrte. */
1675   -PPC_OP(frsqrte)
  1665 +void OPPROTO op_frsqrte (void)
1676 1666 {
1677 1667 do_frsqrte();
1678 1668 RETURN();
1679 1669 }
1680 1670  
1681 1671 /* fsel - fsel. */
1682   -PPC_OP(fsel)
  1672 +void OPPROTO op_fsel (void)
1683 1673 {
1684 1674 do_fsel();
1685 1675 RETURN();
... ... @@ -1687,7 +1677,7 @@ PPC_OP(fsel)
1687 1677  
1688 1678 /*** Floating-Point multiply-and-add ***/
1689 1679 /* fmadd - fmadd. */
1690   -PPC_OP(fmadd)
  1680 +void OPPROTO op_fmadd (void)
1691 1681 {
1692 1682 #if USE_PRECISE_EMULATION
1693 1683 do_fmadd();
... ... @@ -1699,7 +1689,7 @@ PPC_OP(fmadd)
1699 1689 }
1700 1690  
1701 1691 /* fmsub - fmsub. */
1702   -PPC_OP(fmsub)
  1692 +void OPPROTO op_fmsub (void)
1703 1693 {
1704 1694 #if USE_PRECISE_EMULATION
1705 1695 do_fmsub();
... ... @@ -1711,14 +1701,14 @@ PPC_OP(fmsub)
1711 1701 }
1712 1702  
1713 1703 /* fnmadd - fnmadd. - fnmadds - fnmadds. */
1714   -PPC_OP(fnmadd)
  1704 +void OPPROTO op_fnmadd (void)
1715 1705 {
1716 1706 do_fnmadd();
1717 1707 RETURN();
1718 1708 }
1719 1709  
1720 1710 /* fnmsub - fnmsub. */
1721   -PPC_OP(fnmsub)
  1711 +void OPPROTO op_fnmsub (void)
1722 1712 {
1723 1713 do_fnmsub();
1724 1714 RETURN();
... ... @@ -1726,21 +1716,21 @@ PPC_OP(fnmsub)
1726 1716  
1727 1717 /*** Floating-Point round & convert ***/
1728 1718 /* frsp - frsp. */
1729   -PPC_OP(frsp)
  1719 +void OPPROTO op_frsp (void)
1730 1720 {
1731 1721 FT0 = float64_to_float32(FT0, &env->fp_status);
1732 1722 RETURN();
1733 1723 }
1734 1724  
1735 1725 /* fctiw - fctiw. */
1736   -PPC_OP(fctiw)
  1726 +void OPPROTO op_fctiw (void)
1737 1727 {
1738 1728 do_fctiw();
1739 1729 RETURN();
1740 1730 }
1741 1731  
1742 1732 /* fctiwz - fctiwz. */
1743   -PPC_OP(fctiwz)
  1733 +void OPPROTO op_fctiwz (void)
1744 1734 {
1745 1735 do_fctiwz();
1746 1736 RETURN();
... ... @@ -1748,21 +1738,21 @@ PPC_OP(fctiwz)
1748 1738  
1749 1739 #if defined(TARGET_PPC64)
1750 1740 /* fcfid - fcfid. */
1751   -PPC_OP(fcfid)
  1741 +void OPPROTO op_fcfid (void)
1752 1742 {
1753 1743 do_fcfid();
1754 1744 RETURN();
1755 1745 }
1756 1746  
1757 1747 /* fctid - fctid. */
1758   -PPC_OP(fctid)
  1748 +void OPPROTO op_fctid (void)
1759 1749 {
1760 1750 do_fctid();
1761 1751 RETURN();
1762 1752 }
1763 1753  
1764 1754 /* fctidz - fctidz. */
1765   -PPC_OP(fctidz)
  1755 +void OPPROTO op_fctidz (void)
1766 1756 {
1767 1757 do_fctidz();
1768 1758 RETURN();
... ... @@ -1771,14 +1761,14 @@ PPC_OP(fctidz)
1771 1761  
1772 1762 /*** Floating-Point compare ***/
1773 1763 /* fcmpu */
1774   -PPC_OP(fcmpu)
  1764 +void OPPROTO op_fcmpu (void)
1775 1765 {
1776 1766 do_fcmpu();
1777 1767 RETURN();
1778 1768 }
1779 1769  
1780 1770 /* fcmpo */
1781   -PPC_OP(fcmpo)
  1771 +void OPPROTO op_fcmpo (void)
1782 1772 {
1783 1773 do_fcmpo();
1784 1774 RETURN();
... ... @@ -1786,14 +1776,14 @@ PPC_OP(fcmpo)
1786 1776  
1787 1777 /*** Floating-point move ***/
1788 1778 /* fabs */
1789   -PPC_OP(fabs)
  1779 +void OPPROTO op_fabs (void)
1790 1780 {
1791 1781 FT0 = float64_abs(FT0);
1792 1782 RETURN();
1793 1783 }
1794 1784  
1795 1785 /* fnabs */
1796   -PPC_OP(fnabs)
  1786 +void OPPROTO op_fnabs (void)
1797 1787 {
1798 1788 FT0 = float64_abs(FT0);
1799 1789 FT0 = float64_chs(FT0);
... ... @@ -1801,7 +1791,7 @@ PPC_OP(fnabs)
1801 1791 }
1802 1792  
1803 1793 /* fneg */
1804   -PPC_OP(fneg)
  1794 +void OPPROTO op_fneg (void)
1805 1795 {
1806 1796 FT0 = float64_chs(FT0);
1807 1797 RETURN();
... ... @@ -1871,7 +1861,7 @@ void OPPROTO op_td (void)
1871 1861  
1872 1862 #if !defined(CONFIG_USER_ONLY)
1873 1863 /* tlbia */
1874   -PPC_OP(tlbia)
  1864 +void OPPROTO op_tlbia (void)
1875 1865 {
1876 1866 do_tlbia();
1877 1867 RETURN();
... ...
target-ppc/op_helper.c
  View file @3608160
... ... @@ -88,7 +88,7 @@ void do_store_cr (uint32_t mask)
88 88 {
89 89 int i, sh;
90 90  
91   - for (i = 0, sh = 7; i < 8; i++, sh --) {
  91 + for (i = 0, sh = 7; i < 8; i++, sh--) {
92 92 if (mask & (1 << sh))
93 93 env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
94 94 }
... ... @@ -216,8 +216,8 @@ static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
216 216  
217 217 static void neg128 (uint64_t *plow, uint64_t *phigh)
218 218 {
219   - *plow = ~ *plow;
220   - *phigh = ~ *phigh;
  219 + *plow = ~*plow;
  220 + *phigh = ~*phigh;
221 221 add128(plow, phigh, 1, 0);
222 222 }
223 223  
... ... @@ -258,6 +258,7 @@ void do_mul64 (uint64_t *plow, uint64_t *phigh)
258 258 static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
259 259 {
260 260 int sa, sb;
  261 +
261 262 sa = (a < 0);
262 263 if (sa)
263 264 a = -a;
... ... @@ -2493,14 +2494,14 @@ void do_4xx_tlbre_hi (void)
2493 2494  
2494 2495 void do_4xx_tlbsx (void)
2495 2496 {
2496   - T0 = ppcemb_tlb_search(env, T0);
  2497 + T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
2497 2498 }
2498 2499  
2499 2500 void do_4xx_tlbsx_ (void)
2500 2501 {
2501 2502 int tmp = xer_ov;
2502 2503  
2503   - T0 = ppcemb_tlb_search(env, T0);
  2504 + T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
2504 2505 if (T0 != -1)
2505 2506 tmp |= 0x02;
2506 2507 env->crf[0] = tmp;
... ...
target-ppc/op_helper_mem.h
  View file @3608160
... ... @@ -271,7 +271,7 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
271 271 }
272 272 #endif
273 273  
274   -/* PPC 601 specific instructions (POWER bridge) */
  274 +/* PowerPC 601 specific instructions (POWER bridge) */
275 275 // XXX: to be tested
276 276 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
277 277 {
... ...
target-ppc/op_mem.h
  View file @3608160
... ... @@ -517,7 +517,7 @@ void OPPROTO glue(op_lwarx, MEMSUFFIX) (void)
517 517 do_raise_exception(EXCP_ALIGN);
518 518 } else {
519 519 T1 = glue(ldl, MEMSUFFIX)((uint32_t)T0);
520   - regs->reserve = (uint32_t)T0;
  520 + env->reserve = (uint32_t)T0;
521 521 }
522 522 RETURN();
523 523 }
... ... @@ -529,7 +529,7 @@ void OPPROTO glue(op_lwarx_64, MEMSUFFIX) (void)
529 529 do_raise_exception(EXCP_ALIGN);
530 530 } else {
531 531 T1 = glue(ldl, MEMSUFFIX)((uint64_t)T0);
532   - regs->reserve = (uint64_t)T0;
  532 + env->reserve = (uint64_t)T0;
533 533 }
534 534 RETURN();
535 535 }
... ... @@ -540,7 +540,7 @@ void OPPROTO glue(op_ldarx, MEMSUFFIX) (void)
540 540 do_raise_exception(EXCP_ALIGN);
541 541 } else {
542 542 T1 = glue(ldq, MEMSUFFIX)((uint32_t)T0);
543   - regs->reserve = (uint32_t)T0;
  543 + env->reserve = (uint32_t)T0;
544 544 }
545 545 RETURN();
546 546 }
... ... @@ -551,7 +551,7 @@ void OPPROTO glue(op_ldarx_64, MEMSUFFIX) (void)
551 551 do_raise_exception(EXCP_ALIGN);
552 552 } else {
553 553 T1 = glue(ldq, MEMSUFFIX)((uint64_t)T0);
554   - regs->reserve = (uint64_t)T0;
  554 + env->reserve = (uint64_t)T0;
555 555 }
556 556 RETURN();
557 557 }
... ... @@ -563,7 +563,7 @@ void OPPROTO glue(op_lwarx_le, MEMSUFFIX) (void)
563 563 do_raise_exception(EXCP_ALIGN);
564 564 } else {
565 565 T1 = glue(ld32r, MEMSUFFIX)((uint32_t)T0);
566   - regs->reserve = (uint32_t)T0;
  566 + env->reserve = (uint32_t)T0;
567 567 }
568 568 RETURN();
569 569 }
... ... @@ -575,7 +575,7 @@ void OPPROTO glue(op_lwarx_le_64, MEMSUFFIX) (void)
575 575 do_raise_exception(EXCP_ALIGN);
576 576 } else {
577 577 T1 = glue(ld32r, MEMSUFFIX)((uint64_t)T0);
578   - regs->reserve = (uint64_t)T0;
  578 + env->reserve = (uint64_t)T0;
579 579 }
580 580 RETURN();
581 581 }
... ... @@ -586,7 +586,7 @@ void OPPROTO glue(op_ldarx_le, MEMSUFFIX) (void)
586 586 do_raise_exception(EXCP_ALIGN);
587 587 } else {
588 588 T1 = glue(ld64r, MEMSUFFIX)((uint32_t)T0);
589   - regs->reserve = (uint32_t)T0;
  589 + env->reserve = (uint32_t)T0;
590 590 }
591 591 RETURN();
592 592 }
... ... @@ -597,7 +597,7 @@ void OPPROTO glue(op_ldarx_le_64, MEMSUFFIX) (void)
597 597 do_raise_exception(EXCP_ALIGN);
598 598 } else {
599 599 T1 = glue(ld64r, MEMSUFFIX)((uint64_t)T0);
600   - regs->reserve = (uint64_t)T0;
  600 + env->reserve = (uint64_t)T0;
601 601 }
602 602 RETURN();
603 603 }
... ... @@ -609,14 +609,14 @@ void OPPROTO glue(op_stwcx, MEMSUFFIX) (void)
609 609 if (unlikely(T0 & 0x03)) {
610 610 do_raise_exception(EXCP_ALIGN);
611 611 } else {
612   - if (unlikely(regs->reserve != (uint32_t)T0)) {
  612 + if (unlikely(env->reserve != (uint32_t)T0)) {
613 613 env->crf[0] = xer_ov;
614 614 } else {
615 615 glue(stl, MEMSUFFIX)((uint32_t)T0, T1);
616 616 env->crf[0] = xer_ov | 0x02;
617 617 }
618 618 }
619   - regs->reserve = -1;
  619 + env->reserve = -1;
620 620 RETURN();
621 621 }
622 622  
... ... @@ -626,14 +626,14 @@ void OPPROTO glue(op_stwcx_64, MEMSUFFIX) (void)
626 626 if (unlikely(T0 & 0x03)) {
627 627 do_raise_exception(EXCP_ALIGN);
628 628 } else {
629   - if (unlikely(regs->reserve != (uint64_t)T0)) {
  629 + if (unlikely(env->reserve != (uint64_t)T0)) {
630 630 env->crf[0] = xer_ov;
631 631 } else {
632 632 glue(stl, MEMSUFFIX)((uint64_t)T0, T1);
633 633 env->crf[0] = xer_ov | 0x02;
634 634 }
635 635 }
636   - regs->reserve = -1;
  636 + env->reserve = -1;
637 637 RETURN();
638 638 }
639 639  
... ... @@ -642,14 +642,14 @@ void OPPROTO glue(op_stdcx, MEMSUFFIX) (void)
642 642 if (unlikely(T0 & 0x03)) {
643 643 do_raise_exception(EXCP_ALIGN);
644 644 } else {
645   - if (unlikely(regs->reserve != (uint32_t)T0)) {
  645 + if (unlikely(env->reserve != (uint32_t)T0)) {
646 646 env->crf[0] = xer_ov;
647 647 } else {
648 648 glue(stq, MEMSUFFIX)((uint32_t)T0, T1);
649 649 env->crf[0] = xer_ov | 0x02;
650 650 }
651 651 }
652   - regs->reserve = -1;
  652 + env->reserve = -1;
653 653 RETURN();
654 654 }
655 655  
... ... @@ -658,14 +658,14 @@ void OPPROTO glue(op_stdcx_64, MEMSUFFIX) (void)
658 658 if (unlikely(T0 & 0x03)) {
659 659 do_raise_exception(EXCP_ALIGN);
660 660 } else {
661   - if (unlikely(regs->reserve != (uint64_t)T0)) {
  661 + if (unlikely(env->reserve != (uint64_t)T0)) {
662 662 env->crf[0] = xer_ov;
663 663 } else {
664 664 glue(stq, MEMSUFFIX)((uint64_t)T0, T1);
665 665 env->crf[0] = xer_ov | 0x02;
666 666 }
667 667 }
668   - regs->reserve = -1;
  668 + env->reserve = -1;
669 669 RETURN();
670 670 }
671 671 #endif
... ... @@ -675,14 +675,14 @@ void OPPROTO glue(op_stwcx_le, MEMSUFFIX) (void)
675 675 if (unlikely(T0 & 0x03)) {
676 676 do_raise_exception(EXCP_ALIGN);
677 677 } else {
678   - if (unlikely(regs->reserve != (uint32_t)T0)) {
  678 + if (unlikely(env->reserve != (uint32_t)T0)) {
679 679 env->crf[0] = xer_ov;
680 680 } else {
681 681 glue(st32r, MEMSUFFIX)((uint32_t)T0, T1);
682 682 env->crf[0] = xer_ov | 0x02;
683 683 }
684 684 }
685   - regs->reserve = -1;
  685 + env->reserve = -1;
686 686 RETURN();
687 687 }
688 688  
... ... @@ -692,14 +692,14 @@ void OPPROTO glue(op_stwcx_le_64, MEMSUFFIX) (void)
692 692 if (unlikely(T0 & 0x03)) {
693 693 do_raise_exception(EXCP_ALIGN);
694 694 } else {
695   - if (unlikely(regs->reserve != (uint64_t)T0)) {
  695 + if (unlikely(env->reserve != (uint64_t)T0)) {
696 696 env->crf[0] = xer_ov;
697 697 } else {
698 698 glue(st32r, MEMSUFFIX)((uint64_t)T0, T1);
699 699 env->crf[0] = xer_ov | 0x02;
700 700 }
701 701 }
702   - regs->reserve = -1;
  702 + env->reserve = -1;
703 703 RETURN();
704 704 }
705 705  
... ... @@ -708,14 +708,14 @@ void OPPROTO glue(op_stdcx_le, MEMSUFFIX) (void)
708 708 if (unlikely(T0 & 0x03)) {
709 709 do_raise_exception(EXCP_ALIGN);
710 710 } else {
711   - if (unlikely(regs->reserve != (uint32_t)T0)) {
  711 + if (unlikely(env->reserve != (uint32_t)T0)) {
712 712 env->crf[0] = xer_ov;
713 713 } else {
714 714 glue(st64r, MEMSUFFIX)((uint32_t)T0, T1);
715 715 env->crf[0] = xer_ov | 0x02;
716 716 }
717 717 }
718   - regs->reserve = -1;
  718 + env->reserve = -1;
719 719 RETURN();
720 720 }
721 721  
... ... @@ -724,14 +724,14 @@ void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
724 724 if (unlikely(T0 & 0x03)) {
725 725 do_raise_exception(EXCP_ALIGN);
726 726 } else {
727   - if (unlikely(regs->reserve != (uint64_t)T0)) {
  727 + if (unlikely(env->reserve != (uint64_t)T0)) {
728 728 env->crf[0] = xer_ov;
729 729 } else {
730 730 glue(st64r, MEMSUFFIX)((uint64_t)T0, T1);
731 731 env->crf[0] = xer_ov | 0x02;
732 732 }
733 733 }
734   - regs->reserve = -1;
  734 + env->reserve = -1;
735 735 RETURN();
736 736 }
737 737 #endif
... ... @@ -1095,7 +1095,7 @@ static inline void glue(spe_stwwo, MEMSUFFIX) (target_ulong EA, uint64_t data)
1095 1095 }
1096 1096 PPC_SPE_ST_OP(wwo, spe_stwwo);
1097 1097 static inline void glue(spe_stwwo_le, MEMSUFFIX) (target_ulong EA,
1098   - uint64_t data)
  1098 + uint64_t data)
1099 1099 {
1100 1100 glue(st32r, MEMSUFFIX)(EA, data);
1101 1101 }
... ...
target-ppc/op_template.h
  View file @3608160
... ... @@ -21,38 +21,38 @@
21 21 /* General purpose registers moves */
22 22 void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void)
23 23 {
24   - T0 = regs->gpr[REG];
  24 + T0 = env->gpr[REG];
25 25 RETURN();
26 26 }
27 27  
28 28 void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void)
29 29 {
30   - T1 = regs->gpr[REG];
  30 + T1 = env->gpr[REG];
31 31 RETURN();
32 32 }
33 33  
34 34 void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void)
35 35 {
36   - T2 = regs->gpr[REG];
  36 + T2 = env->gpr[REG];
37 37 RETURN();
38 38 }
39 39  
40 40 void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void)
41 41 {
42   - regs->gpr[REG] = T0;
  42 + env->gpr[REG] = T0;
43 43 RETURN();
44 44 }
45 45  
46 46 void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void)
47 47 {
48   - regs->gpr[REG] = T1;
  48 + env->gpr[REG] = T1;
49 49 RETURN();
50 50 }
51 51  
52 52 #if 0 // unused
53 53 void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
54 54 {
55   - regs->gpr[REG] = T2;
  55 + env->gpr[REG] = T2;
56 56 RETURN();
57 57 }
58 58 #endif
... ... @@ -60,40 +60,40 @@ void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
60 60 #if defined(TARGET_PPCEMB)
61 61 void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
62 62 {
63   - T0_64 = regs->gpr[REG];
  63 + T0_64 = env->gpr[REG];
64 64 RETURN();
65 65 }
66 66  
67 67 void OPPROTO glue(op_load_gpr64_T1_gpr, REG) (void)
68 68 {
69   - T1_64 = regs->gpr[REG];
  69 + T1_64 = env->gpr[REG];
70 70 RETURN();
71 71 }
72 72  
73 73 #if 0 // unused
74 74 void OPPROTO glue(op_load_gpr64_T2_gpr, REG) (void)
75 75 {
76   - T2_64 = regs->gpr[REG];
  76 + T2_64 = env->gpr[REG];
77 77 RETURN();
78 78 }
79 79 #endif
80 80  
81 81 void OPPROTO glue(op_store_T0_gpr64_gpr, REG) (void)
82 82 {
83   - regs->gpr[REG] = T0_64;
  83 + env->gpr[REG] = T0_64;
84 84 RETURN();
85 85 }
86 86  
87 87 void OPPROTO glue(op_store_T1_gpr64_gpr, REG) (void)
88 88 {
89   - regs->gpr[REG] = T1_64;
  89 + env->gpr[REG] = T1_64;
90 90 RETURN();
91 91 }
92 92  
93 93 #if 0 // unused
94 94 void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
95 95 {
96   - regs->gpr[REG] = T2_64;
  96 + env->gpr[REG] = T2_64;
97 97 RETURN();
98 98 }
99 99 #endif
... ... @@ -103,57 +103,57 @@ void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
103 103 /* Condition register moves */
104 104 void OPPROTO glue(op_load_crf_T0_crf, REG) (void)
105 105 {
106   - T0 = regs->crf[REG];
  106 + T0 = env->crf[REG];
107 107 RETURN();
108 108 }
109 109  
110 110 void OPPROTO glue(op_load_crf_T1_crf, REG) (void)
111 111 {
112   - T1 = regs->crf[REG];
  112 + T1 = env->crf[REG];
113 113 RETURN();
114 114 }
115 115  
116 116 void OPPROTO glue(op_store_T0_crf_crf, REG) (void)
117 117 {
118   - regs->crf[REG] = T0;
  118 + env->crf[REG] = T0;
119 119 RETURN();
120 120 }
121 121  
122 122 void OPPROTO glue(op_store_T1_crf_crf, REG) (void)
123 123 {
124   - regs->crf[REG] = T1;
  124 + env->crf[REG] = T1;
125 125 RETURN();
126 126 }
127 127  
128 128 /* Floating point condition and status register moves */
129 129 void OPPROTO glue(op_load_fpscr_T0_fpscr, REG) (void)
130 130 {
131   - T0 = regs->fpscr[REG];
  131 + T0 = env->fpscr[REG];
132 132 RETURN();
133 133 }
134 134  
135 135 #if REG == 0
136 136 void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void)
137 137 {
138   - regs->fpscr[REG] = (regs->fpscr[REG] & 0x9) | (T0 & ~0x9);
  138 + env->fpscr[REG] = (env->fpscr[REG] & 0x9) | (T0 & ~0x9);
139 139 RETURN();
140 140 }
141 141  
142 142 void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void)
143 143 {
144   - regs->fpscr[REG] = (regs->fpscr[REG] & 0x9);
  144 + env->fpscr[REG] = (env->fpscr[REG] & 0x9);
145 145 RETURN();
146 146 }
147 147 #else
148 148 void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void)
149 149 {
150   - regs->fpscr[REG] = T0;
  150 + env->fpscr[REG] = T0;
151 151 RETURN();
152 152 }
153 153  
154 154 void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void)
155 155 {
156   - regs->fpscr[REG] = 0x0;
  156 + env->fpscr[REG] = 0x0;
157 157 RETURN();
158 158 }
159 159 #endif
... ...
target-ppc/translate.c
  View file @3608160
... ... @@ -118,7 +118,7 @@ GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
118 118 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
119 119 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
120 120 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
121   -static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
  121 +static inline void gen_op_store_T0_fpscri (int n, uint8_t param)
122 122 {
123 123 gen_op_set_T0(param);
124 124 gen_op_store_T0_fpscr(n);
... ... @@ -1312,7 +1312,7 @@ static inline void gen_rldcl (DisasContext *ctx, int mbn)
1312 1312 mb = MB(ctx->opcode) | (mbn << 5);
1313 1313 gen_rldnm(ctx, mb, 63);
1314 1314 }
1315   -GEN_PPC64_R2(rldcl, 0x1E, 0x08)
  1315 +GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1316 1316 /* rldcr - rldcr. */
1317 1317 static inline void gen_rldcr (DisasContext *ctx, int men)
1318 1318 {
... ... @@ -1321,7 +1321,7 @@ static inline void gen_rldcr (DisasContext *ctx, int men)
1321 1321 me = MB(ctx->opcode) | (men << 5);
1322 1322 gen_rldnm(ctx, 0, me);
1323 1323 }
1324   -GEN_PPC64_R2(rldcr, 0x1E, 0x09)
  1324 +GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1325 1325 /* rldimi - rldimi. */
1326 1326 static inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1327 1327 {
... ... @@ -1355,7 +1355,7 @@ static inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1355 1355 if (unlikely(Rc(ctx->opcode) != 0))
1356 1356 gen_set_Rc0(ctx);
1357 1357 }
1358   -GEN_PPC64_R4(rldimi, 0x1E, 0x06)
  1358 +GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1359 1359 #endif
1360 1360  
1361 1361 /*** Integer shift ***/
... ... @@ -2601,8 +2601,7 @@ GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
2601 2601 }
2602 2602  
2603 2603 /*** Branch ***/
2604   -
2605   -static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
  2604 +static inline void gen_goto_tb (DisasContext *ctx, int n, target_ulong dest)
2606 2605 {
2607 2606 TranslationBlock *tb;
2608 2607 tb = ctx->tb;
... ... @@ -2669,7 +2668,7 @@ GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2669 2668 #define BCOND_LR 1
2670 2669 #define BCOND_CTR 2
2671 2670  
2672   -static inline void gen_bcond(DisasContext *ctx, int type)
  2671 +static inline void gen_bcond (DisasContext *ctx, int type)
2673 2672 {
2674 2673 target_ulong target = 0;
2675 2674 target_ulong li;
... ... @@ -2806,7 +2805,7 @@ static inline void gen_bcond(DisasContext *ctx, int type)
2806 2805 #endif
2807 2806 gen_op_btest_T1(ctx->nip);
2808 2807 gen_op_reset_T0();
2809   - no_test:
  2808 + no_test:
2810 2809 if (ctx->singlestep_enabled)
2811 2810 gen_op_debug();
2812 2811 gen_op_exit_tb();
... ... @@ -5585,9 +5584,9 @@ static inline uint32_t load_xer (CPUState *env)
5585 5584 (xer_cmp << XER_CMP);
5586 5585 }
5587 5586  
5588   -void cpu_dump_state(CPUState *env, FILE *f,
5589   - int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5590   - int flags)
  5587 +void cpu_dump_state (CPUState *env, FILE *f,
  5588 + int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
  5589 + int flags)
5591 5590 {
5592 5591 #if defined(TARGET_PPC64) || 1
5593 5592 #define FILL ""
... ...
target-ppc/translate_init.c
  View file @3608160
... ... @@ -2896,7 +2896,7 @@ static ppc_def_t ppc_defs[] = {
2896 2896 .name = "Npe405H",
2897 2897 .pvr = CPU_PPC_NPE405H,
2898 2898 .pvr_mask = 0xFFFFFFFF,
2899   - .insns_flags = PPC_INSNS_405,
  2899 + .insns_flags = PPC_INSNS_405,
2900 2900 .flags = PPC_FLAGS_405,
2901 2901 .msr_mask = 0x00000000020EFF30ULL,
2902 2902 },
... ... @@ -3000,7 +3000,7 @@ static ppc_def_t ppc_defs[] = {
3000 3000 .msr_mask = 0x00000000020EFF30ULL,
3001 3001 },
3002 3002 #endif
3003   - /* Xilinx PowerPC 405 cores */
  3003 + /* Xilinx PowerPC 405 cores */
3004 3004 #if defined (TODO)
3005 3005 {
3006 3006 .name = "x2vp4",
... ...