gwj / at91sam9263 · Commits

Commit 35fbce2c41f4ae302af51166f62ea48f5e54617d

Authored by aurel32
1 parent 72c3a3ee

target-mips: optimize decode_opc() 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7042 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 17 additions and 13 deletions
target-mips/translate.c
  View file @35fbce2
... ... @@ -7527,7 +7527,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7527 7527 case OPC_MOVCI:
7528 7528 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
7529 7529 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
7530   - save_cpu_state(ctx, 1);
7531 7530 check_cp1_enabled(ctx);
7532 7531 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
7533 7532 (ctx->opcode >> 16) & 1);
... ... @@ -7623,28 +7622,33 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7623 7622 case OPC_RDHWR:
7624 7623 check_insn(env, ctx, ISA_MIPS32R2);
7625 7624 {
7626   - TCGv t0 = tcg_temp_local_new();
  7625 + TCGv t0 = tcg_temp_new();
7627 7626  
7628 7627 switch (rd) {
7629 7628 case 0:
7630 7629 save_cpu_state(ctx, 1);
7631 7630 gen_helper_rdhwr_cpunum(t0);
  7631 + gen_store_gpr(t0, rt);
7632 7632 break;
7633 7633 case 1:
7634 7634 save_cpu_state(ctx, 1);
7635 7635 gen_helper_rdhwr_synci_step(t0);
  7636 + gen_store_gpr(t0, rt);
7636 7637 break;
7637 7638 case 2:
7638 7639 save_cpu_state(ctx, 1);
7639 7640 gen_helper_rdhwr_cc(t0);
  7641 + gen_store_gpr(t0, rt);
7640 7642 break;
7641 7643 case 3:
7642 7644 save_cpu_state(ctx, 1);
7643 7645 gen_helper_rdhwr_ccres(t0);
  7646 + gen_store_gpr(t0, rt);
7644 7647 break;
7645 7648 case 29:
7646 7649 #if defined(CONFIG_USER_ONLY)
7647 7650 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
  7651 + gen_store_gpr(t0, rt);
7648 7652 break;
7649 7653 #else
7650 7654 /* XXX: Some CPUs implement this in hardware.
... ... @@ -7655,15 +7659,14 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7655 7659 generate_exception(ctx, EXCP_RI);
7656 7660 break;
7657 7661 }
7658   - gen_store_gpr(t0, rt);
7659 7662 tcg_temp_free(t0);
7660 7663 }
7661 7664 break;
7662 7665 case OPC_FORK:
7663 7666 check_insn(env, ctx, ASE_MT);
7664 7667 {
7665   - TCGv t0 = tcg_temp_local_new();
7666   - TCGv t1 = tcg_temp_local_new();
  7668 + TCGv t0 = tcg_temp_new();
  7669 + TCGv t1 = tcg_temp_new();
7667 7670  
7668 7671 gen_load_gpr(t0, rt);
7669 7672 gen_load_gpr(t1, rs);
... ... @@ -7675,8 +7678,9 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7675 7678 case OPC_YIELD:
7676 7679 check_insn(env, ctx, ASE_MT);
7677 7680 {
7678   - TCGv t0 = tcg_temp_local_new();
  7681 + TCGv t0 = tcg_temp_new();
7679 7682  
  7683 + save_cpu_state(ctx, 1);
7680 7684 gen_load_gpr(t0, rs);
7681 7685 gen_helper_yield(t0, t0);
7682 7686 gen_store_gpr(t0, rd);
... ... @@ -7748,37 +7752,41 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7748 7752 case OPC_MFMC0:
7749 7753 #ifndef CONFIG_USER_ONLY
7750 7754 {
7751   - TCGv t0 = tcg_temp_local_new();
  7755 + TCGv t0 = tcg_temp_new();
7752 7756  
7753 7757 op2 = MASK_MFMC0(ctx->opcode);
7754 7758 switch (op2) {
7755 7759 case OPC_DMT:
7756 7760 check_insn(env, ctx, ASE_MT);
7757 7761 gen_helper_dmt(t0, t0);
  7762 + gen_store_gpr(t0, rt);
7758 7763 break;
7759 7764 case OPC_EMT:
7760 7765 check_insn(env, ctx, ASE_MT);
7761 7766 gen_helper_emt(t0, t0);
  7767 + gen_store_gpr(t0, rt);
7762 7768 break;
7763 7769 case OPC_DVPE:
7764 7770 check_insn(env, ctx, ASE_MT);
7765 7771 gen_helper_dvpe(t0, t0);
  7772 + gen_store_gpr(t0, rt);
7766 7773 break;
7767 7774 case OPC_EVPE:
7768 7775 check_insn(env, ctx, ASE_MT);
7769 7776 gen_helper_evpe(t0, t0);
  7777 + gen_store_gpr(t0, rt);
7770 7778 break;
7771 7779 case OPC_DI:
7772 7780 check_insn(env, ctx, ISA_MIPS32R2);
7773   - save_cpu_state(ctx, 1);
7774 7781 gen_helper_di(t0);
  7782 + gen_store_gpr(t0, rt);
7775 7783 /* Stop translation as we may have switched the execution mode */
7776 7784 ctx->bstate = BS_STOP;
7777 7785 break;
7778 7786 case OPC_EI:
7779 7787 check_insn(env, ctx, ISA_MIPS32R2);
7780   - save_cpu_state(ctx, 1);
7781 7788 gen_helper_ei(t0);
  7789 + gen_store_gpr(t0, rt);
7782 7790 /* Stop translation as we may have switched the execution mode */
7783 7791 ctx->bstate = BS_STOP;
7784 7792 break;
... ... @@ -7787,7 +7795,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7787 7795 generate_exception(ctx, EXCP_RI);
7788 7796 break;
7789 7797 }
7790   - gen_store_gpr(t0, rt);
7791 7798 tcg_temp_free(t0);
7792 7799 }
7793 7800 #endif /* !CONFIG_USER_ONLY */
... ... @@ -7839,7 +7846,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7839 7846 case OPC_SWC1:
7840 7847 case OPC_SDC1:
7841 7848 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
7842   - save_cpu_state(ctx, 1);
7843 7849 check_cp1_enabled(ctx);
7844 7850 gen_flt_ldst(ctx, op, rt, rs, imm);
7845 7851 } else {
... ... @@ -7849,7 +7855,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7849 7855  
7850 7856 case OPC_CP1:
7851 7857 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
7852   - save_cpu_state(ctx, 1);
7853 7858 check_cp1_enabled(ctx);
7854 7859 op1 = MASK_CP1(ctx->opcode);
7855 7860 switch (op1) {
... ... @@ -7908,7 +7913,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7908 7913  
7909 7914 case OPC_CP3:
7910 7915 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
7911   - save_cpu_state(ctx, 1);
7912 7916 check_cp1_enabled(ctx);
7913 7917 op1 = MASK_CP3(ctx->opcode);
7914 7918 switch (op1) {
... ...