gwj / at91sam9263 · Commits

Commit 35ef81d6d2dd1e49a597e6ef44d0c64951ae933c

Authored by edgar_igl
1 parent c01c07bb

ETRAX: Correct size of control-register area. 

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6209 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 18 additions and 42 deletions
hw/etraxfs_eth.c
  View file @35ef81d
... ... @@ -297,18 +297,18 @@ static void mdio_cycle(struct qemu_mdio *bus)
297 297 /* ETRAX-FS Ethernet MAC block starts here. */
298 298  
299 299 #define RW_MA0_LO 0x00
300   -#define RW_MA0_HI 0x04
301   -#define RW_MA1_LO 0x08
302   -#define RW_MA1_HI 0x0c
303   -#define RW_GA_LO 0x10
304   -#define RW_GA_HI 0x14
305   -#define RW_GEN_CTRL 0x18
306   -#define RW_REC_CTRL 0x1c
307   -#define RW_TR_CTRL 0x20
308   -#define RW_CLR_ERR 0x24
309   -#define RW_MGM_CTRL 0x28
310   -#define R_STAT 0x2c
311   -#define FS_ETH_MAX_REGS 0x5c
  300 +#define RW_MA0_HI 0x01
  301 +#define RW_MA1_LO 0x02
  302 +#define RW_MA1_HI 0x03
  303 +#define RW_GA_LO 0x04
  304 +#define RW_GA_HI 0x05
  305 +#define RW_GEN_CTRL 0x06
  306 +#define RW_REC_CTRL 0x07
  307 +#define RW_TR_CTRL 0x08
  308 +#define RW_CLR_ERR 0x09
  309 +#define RW_MGM_CTRL 0x0a
  310 +#define R_STAT 0x0b
  311 +#define FS_ETH_MAX_REGS 0x17
312 312  
313 313 struct fs_eth
314 314 {
... ... @@ -360,42 +360,25 @@ static void eth_validate_duplex(struct fs_eth *eth)
360 360 }
361 361 }
362 362  
363   -static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr)
364   -{
365   - struct fs_eth *eth = opaque;
366   - CPUState *env = eth->env;
367   - cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
368   - addr);
369   - return 0;
370   -}
371   -
372 363 static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
373 364 {
374 365 struct fs_eth *eth = opaque;
375 366 uint32_t r = 0;
376 367  
  368 + addr >>= 2;
  369 +
377 370 switch (addr) {
378 371 case R_STAT:
379   - /* Attach an MDIO/PHY abstraction. */
380 372 r = eth->mdio_bus.mdio & 1;
381 373 break;
382 374 default:
383 375 r = eth->regs[addr];
384   - D(printf ("%s %x\n", __func__, addr));
  376 + D(printf ("%s %x\n", __func__, addr * 4));
385 377 break;
386 378 }
387 379 return r;
388 380 }
389 381  
390   -static void
391   -eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
392   -{
393   - struct fs_eth *eth = opaque;
394   - CPUState *env = eth->env;
395   - cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
396   - addr);
397   -}
398   -
399 382 static void eth_update_ma(struct fs_eth *eth, int ma)
400 383 {
401 384 int reg;
... ... @@ -425,20 +408,15 @@ eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
425 408 {
426 409 struct fs_eth *eth = opaque;
427 410  
  411 + addr >>= 2;
428 412 switch (addr)
429 413 {
430 414 case RW_MA0_LO:
431   - eth->regs[addr] = value;
432   - eth_update_ma(eth, 0);
433   - break;
434 415 case RW_MA0_HI:
435 416 eth->regs[addr] = value;
436 417 eth_update_ma(eth, 0);
437 418 break;
438 419 case RW_MA1_LO:
439   - eth->regs[addr] = value;
440   - eth_update_ma(eth, 1);
441   - break;
442 420 case RW_MA1_HI:
443 421 eth->regs[addr] = value;
444 422 eth_update_ma(eth, 1);
... ... @@ -553,14 +531,12 @@ static int eth_tx_push(void *opaque, unsigned char *buf, int len)
553 531 }
554 532  
555 533 static CPUReadMemoryFunc *eth_read[] = {
556   - &eth_rinvalid,
557   - &eth_rinvalid,
  534 + NULL, NULL,
558 535 &eth_readl,
559 536 };
560 537  
561 538 static CPUWriteMemoryFunc *eth_write[] = {
562   - &eth_winvalid,
563   - &eth_winvalid,
  539 + NULL, NULL,
564 540 &eth_writel,
565 541 };
566 542  
... ...