gwj / at91sam9263 · Commits

Commit 35b961cf8d8a38e51a05dd9e540d1ddc6e66ffc3

Authored by bellard
1 parent 8ccad811

indent 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2104 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 110 additions and 98 deletions
hw/lance.c
  View file @35b961c
@@ -48,7 +48,7 @@ do { printf("LANCE: " fmt , ##args); } while (0) @@ -48,7 +48,7 @@ do { printf("LANCE: " fmt , ##args); } while (0)
48 #define LE_RDP 0 48 #define LE_RDP 0
49 #define LE_RAP 1 49 #define LE_RAP 1
50 50
51 -#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */ 51 +#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
52 52
53 #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */ 53 #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
54 #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */ 54 #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
@@ -67,36 +67,36 @@ do { printf("LANCE: " fmt , ##args); } while (0) @@ -67,36 +67,36 @@ do { printf("LANCE: " fmt , ##args); } while (0)
67 #define LE_C0_STRT 0x0002 /* Start the card */ 67 #define LE_C0_STRT 0x0002 /* Start the card */
68 #define LE_C0_INIT 0x0001 /* Init the card */ 68 #define LE_C0_INIT 0x0001 /* Init the card */
69 69
70 -#define LE_C3_BSWP 0x4 /* SWAP */ 70 +#define LE_C3_BSWP 0x4 /* SWAP */
71 #define LE_C3_ACON 0x2 /* ALE Control */ 71 #define LE_C3_ACON 0x2 /* ALE Control */
72 #define LE_C3_BCON 0x1 /* Byte control */ 72 #define LE_C3_BCON 0x1 /* Byte control */
73 73
74 /* Receive message descriptor 1 */ 74 /* Receive message descriptor 1 */
75 -#define LE_R1_OWN 0x80 /* Who owns the entry */  
76 -#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */  
77 -#define LE_R1_FRA 0x20 /* FRA: Frame error */  
78 -#define LE_R1_OFL 0x10 /* OFL: Frame overflow */  
79 -#define LE_R1_CRC 0x08 /* CRC error */  
80 -#define LE_R1_BUF 0x04 /* BUF: Buffer error */  
81 -#define LE_R1_SOP 0x02 /* Start of packet */  
82 -#define LE_R1_EOP 0x01 /* End of packet */  
83 -#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */  
84 -  
85 -#define LE_T1_OWN 0x80 /* Lance owns the packet */  
86 -#define LE_T1_ERR 0x40 /* Error summary */  
87 -#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */  
88 -#define LE_T1_EONE 0x08 /* Error: one retry needed */  
89 -#define LE_T1_EDEF 0x04 /* Error: deferred */  
90 -#define LE_T1_SOP 0x02 /* Start of packet */  
91 -#define LE_T1_EOP 0x01 /* End of packet */ 75 +#define LE_R1_OWN 0x80 /* Who owns the entry */
  76 +#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
  77 +#define LE_R1_FRA 0x20 /* FRA: Frame error */
  78 +#define LE_R1_OFL 0x10 /* OFL: Frame overflow */
  79 +#define LE_R1_CRC 0x08 /* CRC error */
  80 +#define LE_R1_BUF 0x04 /* BUF: Buffer error */
  81 +#define LE_R1_SOP 0x02 /* Start of packet */
  82 +#define LE_R1_EOP 0x01 /* End of packet */
  83 +#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
  84 +
  85 +#define LE_T1_OWN 0x80 /* Lance owns the packet */
  86 +#define LE_T1_ERR 0x40 /* Error summary */
  87 +#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
  88 +#define LE_T1_EONE 0x08 /* Error: one retry needed */
  89 +#define LE_T1_EDEF 0x04 /* Error: deferred */
  90 +#define LE_T1_SOP 0x02 /* Start of packet */
  91 +#define LE_T1_EOP 0x01 /* End of packet */
92 #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ 92 #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
93 93
94 -#define LE_T3_BUF 0x8000 /* Buffer error */  
95 -#define LE_T3_UFL 0x4000 /* Error underflow */  
96 -#define LE_T3_LCOL 0x1000 /* Error late collision */  
97 -#define LE_T3_CLOS 0x0800 /* Error carrier loss */  
98 -#define LE_T3_RTY 0x0400 /* Error retry */  
99 -#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */ 94 +#define LE_T3_BUF 0x8000 /* Buffer error */
  95 +#define LE_T3_UFL 0x4000 /* Error underflow */
  96 +#define LE_T3_LCOL 0x1000 /* Error late collision */
  97 +#define LE_T3_CLOS 0x0800 /* Error carrier loss */
  98 +#define LE_T3_RTY 0x0400 /* Error retry */
  99 +#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
100 100
101 #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS)) 101 #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
102 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1) 102 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
@@ -111,43 +111,43 @@ do { printf(&quot;LANCE: &quot; fmt , ##args); } while (0) @@ -111,43 +111,43 @@ do { printf(&quot;LANCE: &quot; fmt , ##args); } while (0)
111 #define TX_BUFF_SIZE PKT_BUF_SZ 111 #define TX_BUFF_SIZE PKT_BUF_SZ
112 112
113 struct lance_rx_desc { 113 struct lance_rx_desc {
114 - unsigned short rmd0; /* low address of packet */  
115 - unsigned char rmd1_bits; /* descriptor bits */  
116 - unsigned char rmd1_hadr; /* high address of packet */  
117 - short length; /* This length is 2s complement (negative)!  
118 - * Buffer length  
119 - */  
120 - unsigned short mblength; /* This is the actual number of bytes received */ 114 + unsigned short rmd0; /* low address of packet */
  115 + unsigned char rmd1_bits; /* descriptor bits */
  116 + unsigned char rmd1_hadr; /* high address of packet */
  117 + short length; /* This length is 2s complement (negative)!
  118 + * Buffer length
  119 + */
  120 + unsigned short mblength; /* This is the actual number of bytes received */
121 }; 121 };
122 122
123 struct lance_tx_desc { 123 struct lance_tx_desc {
124 - unsigned short tmd0; /* low address of packet */  
125 - unsigned char tmd1_bits; /* descriptor bits */  
126 - unsigned char tmd1_hadr; /* high address of packet */  
127 - short length; /* Length is 2s complement (negative)! */  
128 - unsigned short misc; 124 + unsigned short tmd0; /* low address of packet */
  125 + unsigned char tmd1_bits; /* descriptor bits */
  126 + unsigned char tmd1_hadr; /* high address of packet */
  127 + short length; /* Length is 2s complement (negative)! */
  128 + unsigned short misc;
129 }; 129 };
130 130
131 /* The LANCE initialization block, described in databook. */ 131 /* The LANCE initialization block, described in databook. */
132 /* On the Sparc, this block should be on a DMA region */ 132 /* On the Sparc, this block should be on a DMA region */
133 struct lance_init_block { 133 struct lance_init_block {
134 - unsigned short mode; /* Pre-set mode (reg. 15) */  
135 - unsigned char phys_addr[6]; /* Physical ethernet address */  
136 - unsigned filter[2]; /* Multicast filter. */  
137 -  
138 - /* Receive and transmit ring base, along with extra bits. */  
139 - unsigned short rx_ptr; /* receive descriptor addr */  
140 - unsigned short rx_len; /* receive len and high addr */  
141 - unsigned short tx_ptr; /* transmit descriptor addr */  
142 - unsigned short tx_len; /* transmit len and high addr */  
143 -  
144 - /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */  
145 - struct lance_rx_desc brx_ring[RX_RING_SIZE];  
146 - struct lance_tx_desc btx_ring[TX_RING_SIZE];  
147 -  
148 - char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];  
149 - char pad[2]; /* align rx_buf for copy_and_sum(). */  
150 - char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE]; 134 + unsigned short mode; /* Pre-set mode (reg. 15) */
  135 + unsigned char phys_addr[6]; /* Physical ethernet address */
  136 + unsigned filter[2]; /* Multicast filter. */
  137 +
  138 + /* Receive and transmit ring base, along with extra bits. */
  139 + unsigned short rx_ptr; /* receive descriptor addr */
  140 + unsigned short rx_len; /* receive len and high addr */
  141 + unsigned short tx_ptr; /* transmit descriptor addr */
  142 + unsigned short tx_len; /* transmit len and high addr */
  143 +
  144 + /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
  145 + struct lance_rx_desc brx_ring[RX_RING_SIZE];
  146 + struct lance_tx_desc btx_ring[TX_RING_SIZE];
  147 +
  148 + char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE];
  149 + char pad[2]; /* align rx_buf for copy_and_sum(). */
  150 + char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE];
151 }; 151 };
152 152
153 #define LEDMA_REGS 4 153 #define LEDMA_REGS 4
@@ -155,11 +155,11 @@ struct lance_init_block { @@ -155,11 +155,11 @@ struct lance_init_block {
155 155
156 typedef struct LANCEState { 156 typedef struct LANCEState {
157 VLANClientState *vc; 157 VLANClientState *vc;
158 - uint8_t macaddr[6]; /* init mac address */ 158 + uint8_t macaddr[6]; /* init mac address */
159 uint32_t leptr; 159 uint32_t leptr;
160 uint16_t addr; 160 uint16_t addr;
161 uint16_t regs[LE_NREGS]; 161 uint16_t regs[LE_NREGS];
162 - uint8_t phys[6]; /* mac address */ 162 + uint8_t phys[6]; /* mac address */
163 int irq; 163 int irq;
164 unsigned int rxptr, txptr; 164 unsigned int rxptr, txptr;
165 uint32_t ledmaregs[LEDMA_REGS]; 165 uint32_t ledmaregs[LEDMA_REGS];
@@ -192,13 +192,14 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) @@ -192,13 +192,14 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
192 DPRINTF("read areg = %4.4x\n", s->addr); 192 DPRINTF("read areg = %4.4x\n", s->addr);
193 return s->addr; 193 return s->addr;
194 default: 194 default:
195 - DPRINTF("read unknown(%d)\n", saddr>>1); 195 + DPRINTF("read unknown(%d)\n", saddr >> 1);
196 break; 196 break;
197 } 197 }
198 return 0; 198 return 0;
199 } 199 }
200 200
201 -static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) 201 +static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
  202 + uint32_t val)
202 { 203 {
203 LANCEState *s = opaque; 204 LANCEState *s = opaque;
204 uint32_t saddr; 205 uint32_t saddr;
@@ -208,7 +209,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val @@ -208,7 +209,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
208 switch (saddr >> 1) { 209 switch (saddr >> 1) {
209 case LE_RDP: 210 case LE_RDP:
210 DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val); 211 DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
211 - switch(s->addr) { 212 + switch (s->addr) {
212 case LE_CSR0: 213 case LE_CSR0:
213 if (val & LE_C0_STOP) { 214 if (val & LE_C0_STOP) {
214 s->regs[LE_CSR0] = LE_C0_STOP; 215 s->regs[LE_CSR0] = LE_C0_STOP;
@@ -235,8 +236,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val @@ -235,8 +236,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
235 if (val & LE_C0_INIT) { 236 if (val & LE_C0_INIT) {
236 reg |= LE_C0_IDON | LE_C0_INIT; 237 reg |= LE_C0_IDON | LE_C0_INIT;
237 reg &= ~LE_C0_STOP; 238 reg &= ~LE_C0_STOP;
238 - }  
239 - else if (val & LE_C0_STRT) { 239 + } else if (val & LE_C0_STRT) {
240 reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON; 240 reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
241 reg &= ~LE_C0_STOP; 241 reg &= ~LE_C0_STOP;
242 } 242 }
@@ -262,7 +262,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val @@ -262,7 +262,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
262 s->addr = val; 262 s->addr = val;
263 break; 263 break;
264 default: 264 default:
265 - DPRINTF("write unknown(%d) = %4.4x\n", saddr>>1, val); 265 + DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val);
266 break; 266 break;
267 } 267 }
268 lance_send(s); 268 lance_send(s);
@@ -288,7 +288,7 @@ static int lance_can_receive(void *opaque) @@ -288,7 +288,7 @@ static int lance_can_receive(void *opaque)
288 return 1; 288 return 1;
289 } 289 }
290 290
291 -static void lance_receive(void *opaque, const uint8_t *buf, int size) 291 +static void lance_receive(void *opaque, const uint8_t * buf, int size)
292 { 292 {
293 LANCEState *s = opaque; 293 LANCEState *s = opaque;
294 uint32_t dmaptr = s->leptr + s->ledmaregs[3]; 294 uint32_t dmaptr = s->leptr + s->ledmaregs[3];
@@ -304,16 +304,21 @@ static void lance_receive(void *opaque, const uint8_t *buf, int size) @@ -304,16 +304,21 @@ static void lance_receive(void *opaque, const uint8_t *buf, int size)
304 ib = (void *) iommu_translate(dmaptr); 304 ib = (void *) iommu_translate(dmaptr);
305 305
306 old_rxptr = s->rxptr; 306 old_rxptr = s->rxptr;
307 - for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) {  
308 - cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1); 307 + for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK);
  308 + i = (i + 1) & RX_RING_MOD_MASK) {
  309 + cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits,
  310 + (void *) &temp8, 1);
309 if (temp8 == (LE_R1_OWN)) { 311 if (temp8 == (LE_R1_OWN)) {
310 s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK; 312 s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
311 temp16 = size + 4; 313 temp16 = size + 4;
312 bswap16s(&temp16); 314 bswap16s(&temp16);
313 - cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp16, 2);  
314 - cpu_physical_memory_write((uint32_t)&ib->rx_buf[i], buf, size); 315 + cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
  316 + mblength, (void *) &temp16, 2);
  317 + cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf,
  318 + size);
315 temp8 = LE_R1_POK; 319 temp8 = LE_R1_POK;
316 - cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1); 320 + cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
  321 + rmd1_bits, (void *) &temp8, 1);
317 s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR; 322 s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
318 if (s->regs[LE_CSR0] & LE_C0_INEA) 323 if (s->regs[LE_CSR0] & LE_C0_INEA)
319 pic_set_irq(s->irq, 1); 324 pic_set_irq(s->irq, 1);
@@ -339,19 +344,25 @@ static void lance_send(void *opaque) @@ -339,19 +344,25 @@ static void lance_send(void *opaque)
339 344
340 ib = (void *) iommu_translate(dmaptr); 345 ib = (void *) iommu_translate(dmaptr);
341 346
342 - DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr, ib, &ib->btx_ring); 347 + DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n",
  348 + dmaptr, ib, &ib->btx_ring);
343 old_txptr = s->txptr; 349 old_txptr = s->txptr;
344 - for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) {  
345 - cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);  
346 - if (temp8 == (LE_T1_POK|LE_T1_OWN)) {  
347 - cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp16, 2); 350 + for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK);
  351 + i = (i + 1) & TX_RING_MOD_MASK) {
  352 + cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits,
  353 + (void *) &temp8, 1);
  354 + if (temp8 == (LE_T1_POK | LE_T1_OWN)) {
  355 + cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length,
  356 + (void *) &temp16, 2);
348 bswap16s(&temp16); 357 bswap16s(&temp16);
349 temp16 = (~temp16) + 1; 358 temp16 = (~temp16) + 1;
350 - cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp16); 359 + cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf,
  360 + temp16);
351 DPRINTF("sending packet, len %d\n", temp16); 361 DPRINTF("sending packet, len %d\n", temp16);
352 qemu_send_packet(s->vc, pkt_buf, temp16); 362 qemu_send_packet(s->vc, pkt_buf, temp16);
353 temp8 = LE_T1_POK; 363 temp8 = LE_T1_POK;
354 - cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1); 364 + cpu_physical_memory_write((uint32_t) & ib->btx_ring[i].
  365 + tmd1_bits, (void *) &temp8, 1);
355 s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK; 366 s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
356 s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR; 367 s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
357 } 368 }
@@ -369,7 +380,8 @@ static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr) @@ -369,7 +380,8 @@ static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
369 return s->ledmaregs[saddr]; 380 return s->ledmaregs[saddr];
370 } 381 }
371 382
372 -static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 383 +static void ledma_mem_writel(void *opaque, target_phys_addr_t addr,
  384 + uint32_t val)
373 { 385 {
374 LANCEState *s = opaque; 386 LANCEState *s = opaque;
375 uint32_t saddr; 387 uint32_t saddr;
@@ -390,73 +402,73 @@ static CPUWriteMemoryFunc *ledma_mem_write[3] = { @@ -390,73 +402,73 @@ static CPUWriteMemoryFunc *ledma_mem_write[3] = {
390 ledma_mem_writel, 402 ledma_mem_writel,
391 }; 403 };
392 404
393 -static void lance_save(QEMUFile *f, void *opaque) 405 +static void lance_save(QEMUFile * f, void *opaque)
394 { 406 {
395 LANCEState *s = opaque; 407 LANCEState *s = opaque;
396 int i; 408 int i;
397 - 409 +
398 qemu_put_be32s(f, &s->leptr); 410 qemu_put_be32s(f, &s->leptr);
399 qemu_put_be16s(f, &s->addr); 411 qemu_put_be16s(f, &s->addr);
400 - for (i = 0; i < LE_NREGS; i ++) 412 + for (i = 0; i < LE_NREGS; i++)
401 qemu_put_be16s(f, &s->regs[i]); 413 qemu_put_be16s(f, &s->regs[i]);
402 qemu_put_buffer(f, s->phys, 6); 414 qemu_put_buffer(f, s->phys, 6);
403 qemu_put_be32s(f, &s->irq); 415 qemu_put_be32s(f, &s->irq);
404 - for (i = 0; i < LEDMA_REGS; i ++) 416 + for (i = 0; i < LEDMA_REGS; i++)
405 qemu_put_be32s(f, &s->ledmaregs[i]); 417 qemu_put_be32s(f, &s->ledmaregs[i]);
406 } 418 }
407 419
408 -static int lance_load(QEMUFile *f, void *opaque, int version_id) 420 +static int lance_load(QEMUFile * f, void *opaque, int version_id)
409 { 421 {
410 LANCEState *s = opaque; 422 LANCEState *s = opaque;
411 int i; 423 int i;
412 - 424 +
413 if (version_id != 1) 425 if (version_id != 1)
414 - return -EINVAL; 426 + return -EINVAL;
415 427
416 qemu_get_be32s(f, &s->leptr); 428 qemu_get_be32s(f, &s->leptr);
417 qemu_get_be16s(f, &s->addr); 429 qemu_get_be16s(f, &s->addr);
418 - for (i = 0; i < LE_NREGS; i ++) 430 + for (i = 0; i < LE_NREGS; i++)
419 qemu_get_be16s(f, &s->regs[i]); 431 qemu_get_be16s(f, &s->regs[i]);
420 qemu_get_buffer(f, s->phys, 6); 432 qemu_get_buffer(f, s->phys, 6);
421 qemu_get_be32s(f, &s->irq); 433 qemu_get_be32s(f, &s->irq);
422 - for (i = 0; i < LEDMA_REGS; i ++) 434 + for (i = 0; i < LEDMA_REGS; i++)
423 qemu_get_be32s(f, &s->ledmaregs[i]); 435 qemu_get_be32s(f, &s->ledmaregs[i]);
424 return 0; 436 return 0;
425 } 437 }
426 438
427 -void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr) 439 +void lance_init(NICInfo * nd, int irq, uint32_t leaddr, uint32_t ledaddr)
428 { 440 {
429 LANCEState *s; 441 LANCEState *s;
430 int lance_io_memory, ledma_io_memory; 442 int lance_io_memory, ledma_io_memory;
431 443
432 s = qemu_mallocz(sizeof(LANCEState)); 444 s = qemu_mallocz(sizeof(LANCEState));
433 if (!s) 445 if (!s)
434 - return; 446 + return;
435 447
436 s->irq = irq; 448 s->irq = irq;
437 449
438 - lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s); 450 + lance_io_memory =
  451 + cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
439 cpu_register_physical_memory(leaddr, 4, lance_io_memory); 452 cpu_register_physical_memory(leaddr, 4, lance_io_memory);
440 453
441 - ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s); 454 + ledma_io_memory =
  455 + cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
442 cpu_register_physical_memory(ledaddr, 16, ledma_io_memory); 456 cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);
443 457
444 memcpy(s->macaddr, nd->macaddr, 6); 458 memcpy(s->macaddr, nd->macaddr, 6);
445 459
446 lance_reset(s); 460 lance_reset(s);
447 461
448 - s->vc = qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, s); 462 + s->vc =
  463 + qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive,
  464 + s);
449 465
450 snprintf(s->vc->info_str, sizeof(s->vc->info_str), 466 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
451 - "lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",  
452 - s->macaddr[0],  
453 - s->macaddr[1],  
454 - s->macaddr[2],  
455 - s->macaddr[3],  
456 - s->macaddr[4],  
457 - s->macaddr[5]); 467 + "lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
  468 + s->macaddr[0],
  469 + s->macaddr[1],
  470 + s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]);
458 471
459 register_savevm("lance", leaddr, 1, lance_save, lance_load, s); 472 register_savevm("lance", leaddr, 1, lance_save, lance_load, s);
460 qemu_register_reset(lance_reset, s); 473 qemu_register_reset(lance_reset, s);
461 } 474 }
462 -