gwj / at91sam9263 · Commits

Commit 3594c774873fb51fe119c214e78273f43e2556f8

Authored by ths
1 parent 32801d54

Replace TLSZ with TARGET_FMT_lx. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2444 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 7 changed files with 40 additions and 47 deletions
hw/mips_malta.c
  View file @3594c77
... ... @@ -160,7 +160,7 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
160 160  
161 161 default:
162 162 #if 0
163   - printf ("malta_fpga_read: Bad register offset 0x" TLSZ "\n",
  163 + printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
164 164 addr);
165 165 #endif
166 166 break;
... ... @@ -244,7 +244,7 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
244 244  
245 245 default:
246 246 #if 0
247   - printf ("malta_fpga_write: Bad register offset 0x" TLSZ "\n",
  247 + printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
248 248 addr);
249 249 #endif
250 250 break;
... ... @@ -464,7 +464,7 @@ static int64_t load_kernel (CPUState *env)
464 464 /* Store command line. */
465 465 prom_set(index++, env->kernel_filename);
466 466 if (initrd_size > 0)
467   - prom_set(index++, "rd_start=0x" TLSZ " rd_size=%li %s", INITRD_LOAD_ADDR, initrd_size, env->kernel_cmdline);
  467 + prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", INITRD_LOAD_ADDR, initrd_size, env->kernel_cmdline);
468 468 else
469 469 prom_set(index++, env->kernel_cmdline);
470 470  
... ...
hw/mips_r4k.c
  View file @3594c77
... ... @@ -103,7 +103,7 @@ void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
103 103 if (initrd_size > 0) {
104 104 int ret;
105 105 ret = sprintf(phys_ram_base + (16 << 20) - 256,
106   - "rd_start=0x" TLSZ " rd_size=%li ",
  106 + "rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
107 107 INITRD_LOAD_ADDR,
108 108 initrd_size);
109 109 strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
... ...
target-mips/cpu.h
  View file @3594c77
... ... @@ -17,13 +17,6 @@ typedef unsigned char uint_fast8_t;
17 17 typedef unsigned int uint_fast16_t;
18 18 #endif
19 19  
20   -/* target_ulong size spec */
21   -#ifdef MIPS_HAS_MIPS64
22   -#define TLSZ "%016llx"
23   -#else
24   -#define TLSZ "%08x"
25   -#endif
26   -
27 20 typedef union fpr_t fpr_t;
28 21 union fpr_t {
29 22 float64 fd; /* ieee double precision */
... ...
target-mips/helper.c
  View file @3594c77
... ... @@ -132,7 +132,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
132 132 }
133 133 #if 0
134 134 if (logfile) {
135   - fprintf(logfile, TLSZ " %d %d => " TLSZ " %d (%d)\n",
  135 + fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
136 136 address, rw, access_type, *physical, *prot, ret);
137 137 }
138 138 #endif
... ... @@ -174,7 +174,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
174 174 #if 0
175 175 cpu_dump_state(env, logfile, fprintf, 0);
176 176 #endif
177   - fprintf(logfile, "%s pc " TLSZ " ad " TLSZ " rw %d is_user %d smmu %d\n",
  177 + fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
178 178 __func__, env->PC, address, rw, is_user, is_softmmu);
179 179 }
180 180  
... ... @@ -192,7 +192,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
192 192 ret = get_physical_address(env, &physical, &prot,
193 193 address, rw, access_type);
194 194 if (logfile) {
195   - fprintf(logfile, "%s address=" TLSZ " ret %d physical " TLSZ " prot %d\n",
  195 + fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
196 196 __func__, address, ret, physical, prot);
197 197 }
198 198 if (ret == TLBRET_MATCH) {
... ... @@ -258,7 +258,7 @@ void do_interrupt (CPUState *env)
258 258 int cause = -1;
259 259  
260 260 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
261   - fprintf(logfile, "%s enter: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n",
  261 + fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
262 262 __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
263 263 }
264 264 if (env->exception_index == EXCP_EXT_INTERRUPT &&
... ... @@ -410,8 +410,8 @@ void do_interrupt (CPUState *env)
410 410 exit(1);
411 411 }
412 412 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
413   - fprintf(logfile, "%s: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n"
414   - " S %08x C %08x A " TLSZ " D " TLSZ "\n",
  413 + fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
  414 + " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
415 415 __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
416 416 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
417 417 env->CP0_DEPC);
... ...
target-mips/op_helper.c
  View file @3594c77
... ... @@ -492,13 +492,13 @@ void do_tlbr (void)
492 492 void dump_ldst (const unsigned char *func)
493 493 {
494 494 if (loglevel)
495   - fprintf(logfile, "%s => " TLSZ " " TLSZ "\n", __func__, T0, T1);
  495 + fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
496 496 }
497 497  
498 498 void dump_sc (void)
499 499 {
500 500 if (loglevel) {
501   - fprintf(logfile, "%s " TLSZ " at " TLSZ " (" TLSZ ")\n", __func__,
  501 + fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
502 502 T1, T0, env->CP0_LLAddr);
503 503 }
504 504 }
... ... @@ -506,7 +506,7 @@ void dump_sc (void)
506 506 void debug_eret (void)
507 507 {
508 508 if (loglevel) {
509   - fprintf(logfile, "ERET: pc " TLSZ " EPC " TLSZ " ErrorEPC " TLSZ " (%d)\n",
  509 + fprintf(logfile, "ERET: pc " TARGET_FMT_lx " EPC " TARGET_FMT_lx " ErrorEPC " TARGET_FMT_lx " (%d)\n",
510 510 env->PC, env->CP0_EPC, env->CP0_ErrorEPC,
511 511 env->hflags & MIPS_HFLAG_ERL ? 1 : 0);
512 512 }
... ...
target-mips/op_helper_mem.c
  View file @3594c77
... ... @@ -28,7 +28,7 @@ void glue(do_lwl, MEMSUFFIX) (uint32_t tmp)
28 28 }
29 29 #if defined (DEBUG_OP)
30 30 if (logfile) {
31   - fprintf(logfile, "%s: " TLSZ " - %08x " TLSZ " => " TLSZ "\n",
  31 + fprintf(logfile, "%s: " TARGET_FMT_lx " - %08x " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
32 32 __func__, sav, tmp, T1, T0);
33 33 }
34 34 #endif
... ... @@ -57,7 +57,7 @@ void glue(do_lwr, MEMSUFFIX) (uint32_t tmp)
57 57 }
58 58 #if defined (DEBUG_OP)
59 59 if (logfile) {
60   - fprintf(logfile, "%s: " TLSZ " - %08x " TLSZ " => " TLSZ "\n",
  60 + fprintf(logfile, "%s: " TARGET_FMT_lx " - %08x " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
61 61 __func__, sav, tmp, T1, T0);
62 62 }
63 63 #endif
... ... @@ -86,7 +86,7 @@ uint32_t glue(do_swl, MEMSUFFIX) (uint32_t tmp)
86 86 }
87 87 #if defined (DEBUG_OP)
88 88 if (logfile) {
89   - fprintf(logfile, "%s: " TLSZ " - " TLSZ " " TLSZ " => %08x\n",
  89 + fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => %08x\n",
90 90 __func__, T0, sav, T1, tmp);
91 91 }
92 92 #endif
... ... @@ -116,7 +116,7 @@ uint32_t glue(do_swr, MEMSUFFIX) (uint32_t tmp)
116 116 }
117 117 #if defined (DEBUG_OP)
118 118 if (logfile) {
119   - fprintf(logfile, "%s: " TLSZ " - " TLSZ " " TLSZ " => %08x\n",
  119 + fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => %08x\n",
120 120 __func__, T0, sav, T1, tmp);
121 121 }
122 122 #endif
... ... @@ -166,7 +166,7 @@ void glue(do_ldl, MEMSUFFIX) (uint64_t tmp)
166 166 }
167 167 #if defined (DEBUG_OP)
168 168 if (logfile) {
169   - fprintf(logfile, "%s: " TLSZ " - " TLSZ " " TLSZ " => " TLSZ "\n",
  169 + fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
170 170 __func__, sav, tmp, T1, T0);
171 171 }
172 172 #endif
... ... @@ -207,7 +207,7 @@ void glue(do_ldr, MEMSUFFIX) (uint64_t tmp)
207 207 }
208 208 #if defined (DEBUG_OP)
209 209 if (logfile) {
210   - fprintf(logfile, "%s: " TLSZ " - " TLSZ " " TLSZ " => " TLSZ "\n",
  210 + fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
211 211 __func__, sav, tmp, T1, T0);
212 212 }
213 213 #endif
... ... @@ -248,7 +248,7 @@ uint64_t glue(do_sdl, MEMSUFFIX) (uint64_t tmp)
248 248 }
249 249 #if defined (DEBUG_OP)
250 250 if (logfile) {
251   - fprintf(logfile, "%s: " TLSZ " - " TLSZ " " TLSZ " => " TLSZ "\n",
  251 + fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
252 252 __func__, T0, sav, T1, tmp);
253 253 }
254 254 #endif
... ... @@ -290,7 +290,7 @@ uint64_t glue(do_sdr, MEMSUFFIX) (uint64_t tmp)
290 290 }
291 291 #if defined (DEBUG_OP)
292 292 if (logfile) {
293   - fprintf(logfile, "%s: " TLSZ " - " TLSZ " " TLSZ " => " TLSZ "\n",
  293 + fprintf(logfile, "%s: " TARGET_FMT_lx " - " TARGET_FMT_lx " " TARGET_FMT_lx " => " TARGET_FMT_lx "\n",
294 294 __func__, T0, sav, T1, tmp);
295 295 }
296 296 #endif
... ...
target-mips/translate.c
  View file @3594c77
... ... @@ -503,7 +503,7 @@ enum {
503 503 #define MIPS_DEBUG(fmt, args...) \
504 504 do { \
505 505 if (loglevel & CPU_LOG_TB_IN_ASM) { \
506   - fprintf(logfile, TLSZ ": %08x " fmt "\n", \
  506 + fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
507 507 ctx->pc, ctx->opcode , ##args); \
508 508 } \
509 509 } while (0)
... ... @@ -4124,21 +4124,21 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
4124 4124 switch (op) {
4125 4125 case OPC_BC1F:
4126 4126 gen_op_bc1f();
4127   - MIPS_DEBUG("bc1f " TLSZ, btarget);
  4127 + MIPS_DEBUG("bc1f " TARGET_FMT_lx, btarget);
4128 4128 goto not_likely;
4129 4129 case OPC_BC1FL:
4130 4130 gen_op_bc1f();
4131   - MIPS_DEBUG("bc1fl " TLSZ, btarget);
  4131 + MIPS_DEBUG("bc1fl " TARGET_FMT_lx, btarget);
4132 4132 goto likely;
4133 4133 case OPC_BC1T:
4134 4134 gen_op_bc1t();
4135   - MIPS_DEBUG("bc1t " TLSZ, btarget);
  4135 + MIPS_DEBUG("bc1t " TARGET_FMT_lx, btarget);
4136 4136 not_likely:
4137 4137 ctx->hflags |= MIPS_HFLAG_BC;
4138 4138 break;
4139 4139 case OPC_BC1TL:
4140 4140 gen_op_bc1t();
4141   - MIPS_DEBUG("bc1tl " TLSZ, btarget);
  4141 + MIPS_DEBUG("bc1tl " TARGET_FMT_lx, btarget);
4142 4142 likely:
4143 4143 ctx->hflags |= MIPS_HFLAG_BL;
4144 4144 break;
... ... @@ -4149,7 +4149,7 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
4149 4149 }
4150 4150 gen_op_set_bcond();
4151 4151  
4152   - MIPS_DEBUG("enter ds: cond %02x target " TLSZ,
  4152 + MIPS_DEBUG("enter ds: cond %02x target " TARGET_FMT_lx,
4153 4153 ctx->hflags, btarget);
4154 4154 ctx->btarget = btarget;
4155 4155  
... ... @@ -4583,7 +4583,7 @@ static void decode_opc (DisasContext *ctx)
4583 4583  
4584 4584 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
4585 4585 /* Handle blikely not taken case */
4586   - MIPS_DEBUG("blikely condition (" TLSZ ")", ctx->pc + 4);
  4586 + MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
4587 4587 gen_blikely(ctx);
4588 4588 }
4589 4589 op = MASK_OP_MAJOR(ctx->opcode);
... ... @@ -5191,7 +5191,7 @@ void fpu_dump_state(CPUState *env, FILE *f,
5191 5191 void dump_fpu (CPUState *env)
5192 5192 {
5193 5193 if (loglevel) {
5194   - fprintf(logfile, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
  5194 + fprintf(logfile, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
5195 5195 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
5196 5196 fpu_dump_state(env, logfile, fprintf, 0);
5197 5197 }
... ... @@ -5212,23 +5212,23 @@ void cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
5212 5212 int i;
5213 5213  
5214 5214 if (!SIGN_EXT_P(env->PC))
5215   - cpu_fprintf(f, "BROKEN: pc=0x" TLSZ "\n", env->PC);
  5215 + cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->PC);
5216 5216 if (!SIGN_EXT_P(env->HI))
5217   - cpu_fprintf(f, "BROKEN: HI=0x" TLSZ "\n", env->HI);
  5217 + cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI);
5218 5218 if (!SIGN_EXT_P(env->LO))
5219   - cpu_fprintf(f, "BROKEN: LO=0x" TLSZ "\n", env->LO);
  5219 + cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO);
5220 5220 if (!SIGN_EXT_P(env->btarget))
5221   - cpu_fprintf(f, "BROKEN: btarget=0x" TLSZ "\n", env->btarget);
  5221 + cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget);
5222 5222  
5223 5223 for (i = 0; i < 32; i++) {
5224 5224 if (!SIGN_EXT_P(env->gpr[i]))
5225   - cpu_fprintf(f, "BROKEN: %s=0x" TLSZ "\n", regnames[i], env->gpr[i]);
  5225 + cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[i]);
5226 5226 }
5227 5227  
5228 5228 if (!SIGN_EXT_P(env->CP0_EPC))
5229   - cpu_fprintf(f, "BROKEN: EPC=0x" TLSZ "\n", env->CP0_EPC);
  5229 + cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC);
5230 5230 if (!SIGN_EXT_P(env->CP0_LLAddr))
5231   - cpu_fprintf(f, "BROKEN: LLAddr=0x" TLSZ "\n", env->CP0_LLAddr);
  5231 + cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->CP0_LLAddr);
5232 5232 }
5233 5233 #endif
5234 5234  
... ... @@ -5239,12 +5239,12 @@ void cpu_dump_state (CPUState *env, FILE *f,
5239 5239 uint32_t c0_status;
5240 5240 int i;
5241 5241  
5242   - cpu_fprintf(f, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
  5242 + cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
5243 5243 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
5244 5244 for (i = 0; i < 32; i++) {
5245 5245 if ((i & 3) == 0)
5246 5246 cpu_fprintf(f, "GPR%02d:", i);
5247   - cpu_fprintf(f, " %s " TLSZ, regnames[i], env->gpr[i]);
  5247 + cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]);
5248 5248 if ((i & 3) == 3)
5249 5249 cpu_fprintf(f, "\n");
5250 5250 }
... ... @@ -5257,9 +5257,9 @@ void cpu_dump_state (CPUState *env, FILE *f,
5257 5257 if (env->hflags & MIPS_HFLAG_EXL)
5258 5258 c0_status |= (1 << CP0St_EXL);
5259 5259  
5260   - cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TLSZ "\n",
  5260 + cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
5261 5261 c0_status, env->CP0_Cause, env->CP0_EPC);
5262   - cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TLSZ "\n",
  5262 + cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
5263 5263 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
5264 5264 #ifdef MIPS_USES_FPU
5265 5265 if (c0_status & (1 << CP0St_CU1))
... ...