gwj / at91sam9263 · Commits

Commit 356265ae4a865dc384f4985f2498374dac2b3dc8

Authored by ths
1 parent c60e08d9

Static'ify some functions, and use standard inline in translate.c. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4813 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 22 additions and 22 deletions
target-mips/translate.c
  View file @356265a
... ... @@ -757,7 +757,7 @@ FOP_CONDS(abs, ps)
757 757  
758 758 /* Tests */
759 759 #define OP_COND(name, cond) \
760   -void glue(gen_op_, name) (TCGv t0, TCGv t1) \
  760 +static inline void glue(gen_op_, name) (TCGv t0, TCGv t1) \
761 761 { \
762 762 int l1 = gen_new_label(); \
763 763 int l2 = gen_new_label(); \
... ... @@ -778,7 +778,7 @@ OP_COND(ltu, TCG_COND_LTU);
778 778 #undef OP_COND
779 779  
780 780 #define OP_CONDI(name, cond) \
781   -void glue(gen_op_, name) (TCGv t, target_ulong val) \
  781 +static inline void glue(gen_op_, name) (TCGv t, target_ulong val) \
782 782 { \
783 783 int l1 = gen_new_label(); \
784 784 int l2 = gen_new_label(); \
... ... @@ -795,7 +795,7 @@ OP_CONDI(ltiu, TCG_COND_LTU);
795 795 #undef OP_CONDI
796 796  
797 797 #define OP_CONDZ(name, cond) \
798   -void glue(gen_op_, name) (TCGv t) \
  798 +static inline void glue(gen_op_, name) (TCGv t) \
799 799 { \
800 800 int l1 = gen_new_label(); \
801 801 int l2 = gen_new_label(); \
... ... @@ -822,7 +822,7 @@ static inline void gen_save_pc(target_ulong pc)
822 822 tcg_temp_free(r_tmp);
823 823 }
824 824  
825   -static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
  825 +static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
826 826 {
827 827 #if defined MIPS_DEBUG_DISAS
828 828 if (loglevel & CPU_LOG_TB_IN_ASM) {
... ... @@ -853,7 +853,7 @@ static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
853 853 }
854 854 }
855 855  
856   -static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
  856 +static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
857 857 {
858 858 ctx->saved_hflags = ctx->hflags;
859 859 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
... ... @@ -867,7 +867,7 @@ static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
867 867 }
868 868 }
869 869  
870   -static always_inline void
  870 +static inline void
871 871 generate_exception_err (DisasContext *ctx, int excp, int err)
872 872 {
873 873 save_cpu_state(ctx, 1);
... ... @@ -876,7 +876,7 @@ generate_exception_err (DisasContext *ctx, int excp, int err)
876 876 tcg_gen_exit_tb(0);
877 877 }
878 878  
879   -static always_inline void
  879 +static inline void
880 880 generate_exception (DisasContext *ctx, int excp)
881 881 {
882 882 save_cpu_state(ctx, 1);
... ... @@ -911,13 +911,13 @@ static inline void gen_op_addr_add (TCGv t0, TCGv t1)
911 911 #endif
912 912 }
913 913  
914   -static always_inline void check_cp0_enabled(DisasContext *ctx)
  914 +static inline void check_cp0_enabled(DisasContext *ctx)
915 915 {
916 916 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
917 917 generate_exception_err(ctx, EXCP_CpU, 1);
918 918 }
919 919  
920   -static always_inline void check_cp1_enabled(DisasContext *ctx)
  920 +static inline void check_cp1_enabled(DisasContext *ctx)
921 921 {
922 922 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
923 923 generate_exception_err(ctx, EXCP_CpU, 1);
... ... @@ -927,7 +927,7 @@ static always_inline void check_cp1_enabled(DisasContext *ctx)
927 927 This is associated with the nabla symbol in the MIPS32 and MIPS64
928 928 opcode tables. */
929 929  
930   -static always_inline void check_cop1x(DisasContext *ctx)
  930 +static inline void check_cop1x(DisasContext *ctx)
931 931 {
932 932 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
933 933 generate_exception(ctx, EXCP_RI);
... ... @@ -936,7 +936,7 @@ static always_inline void check_cop1x(DisasContext *ctx)
936 936 /* Verify that the processor is running with 64-bit floating-point
937 937 operations enabled. */
938 938  
939   -static always_inline void check_cp1_64bitmode(DisasContext *ctx)
  939 +static inline void check_cp1_64bitmode(DisasContext *ctx)
940 940 {
941 941 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
942 942 generate_exception(ctx, EXCP_RI);
... ... @@ -953,7 +953,7 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx)
953 953 * Multiple 64 bit wide registers can be checked by calling
954 954 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
955 955 */
956   -void check_cp1_registers(DisasContext *ctx, int regs)
  956 +static inline void check_cp1_registers(DisasContext *ctx, int regs)
957 957 {
958 958 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
959 959 generate_exception(ctx, EXCP_RI);
... ... @@ -961,7 +961,7 @@ void check_cp1_registers(DisasContext *ctx, int regs)
961 961  
962 962 /* This code generates a "reserved instruction" exception if the
963 963 CPU does not support the instruction set corresponding to flags. */
964   -static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
  964 +static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
965 965 {
966 966 if (unlikely(!(env->insn_flags & flags)))
967 967 generate_exception(ctx, EXCP_RI);
... ... @@ -969,7 +969,7 @@ static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags
969 969  
970 970 /* This code generates a "reserved instruction" exception if 64-bit
971 971 instructions are not enabled. */
972   -static always_inline void check_mips_64(DisasContext *ctx)
  972 +static inline void check_mips_64(DisasContext *ctx)
973 973 {
974 974 if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
975 975 generate_exception(ctx, EXCP_RI);
... ... @@ -977,7 +977,7 @@ static always_inline void check_mips_64(DisasContext *ctx)
977 977  
978 978 /* load/store instructions. */
979 979 #define OP_LD(insn,fname) \
980   -void inline op_ldst_##insn(TCGv t0, DisasContext *ctx) \
  980 +static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
981 981 { \
982 982 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
983 983 }
... ... @@ -993,7 +993,7 @@ OP_LD(ld,ld64);
993 993 #undef OP_LD
994 994  
995 995 #define OP_ST(insn,fname) \
996   -void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
  996 +static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
997 997 { \
998 998 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
999 999 }
... ... @@ -1006,7 +1006,7 @@ OP_ST(sd,st64);
1006 1006 #undef OP_ST
1007 1007  
1008 1008 #define OP_LD_ATOMIC(insn,fname) \
1009   -void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
  1009 +static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1010 1010 { \
1011 1011 tcg_gen_mov_tl(t1, t0); \
1012 1012 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
... ... @@ -1019,7 +1019,7 @@ OP_LD_ATOMIC(lld,ld64);
1019 1019 #undef OP_LD_ATOMIC
1020 1020  
1021 1021 #define OP_ST_ATOMIC(insn,fname,almask) \
1022   -void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
  1022 +static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1023 1023 { \
1024 1024 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
1025 1025 int l1 = gen_new_label(); \
... ... @@ -1213,7 +1213,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1213 1213  
1214 1214 /* Load and store */
1215 1215 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1216   - int base, int16_t offset)
  1216 + int base, int16_t offset)
1217 1217 {
1218 1218 const char *opn = "flt_ldst";
1219 1219 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
... ... @@ -2459,7 +2459,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
2459 2459 tcg_temp_free(t1);
2460 2460 }
2461 2461  
2462   -static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
  2462 +static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2463 2463 {
2464 2464 TranslationBlock *tb;
2465 2465 tb = ctx->tb;
... ... @@ -2720,7 +2720,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2720 2720  
2721 2721 /* special3 bitfield operations */
2722 2722 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2723   - int rs, int lsb, int msb)
  2723 + int rs, int lsb, int msb)
2724 2724 {
2725 2725 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
2726 2726 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
... ... @@ -7808,7 +7808,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
7808 7808 }
7809 7809 }
7810 7810  
7811   -static always_inline int
  7811 +static inline int
7812 7812 gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7813 7813 int search_pc)
7814 7814 {
... ...