gwj / at91sam9263 · Commits

Commit 3529b538ce91df31b7300ce2fbd838a2ca36e1fc

Authored by ths
1 parent 1579a72e

Fix disabling of the Cause register for R2. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2612 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 11 additions and 11 deletions
hw/mips_timer.c
  View file @3529b53
@@ -22,14 +22,11 @@ uint32_t cpu_mips_get_count (CPUState *env) @@ -22,14 +22,11 @@ uint32_t cpu_mips_get_count (CPUState *env)
22 100 * 1000 * 1000, ticks_per_sec); 22 100 * 1000 * 1000, ticks_per_sec);
23 } 23 }
24 24
25 -static void cpu_mips_update_count (CPUState *env, uint32_t count,  
26 - uint32_t compare) 25 +void cpu_mips_store_count (CPUState *env, uint32_t count)
27 { 26 {
28 uint64_t now, next; 27 uint64_t now, next;
29 uint32_t tmp; 28 uint32_t tmp;
30 -  
31 - if (env->CP0_Cause & (1 << CP0Ca_DC))  
32 - return; 29 + uint32_t compare = env->CP0_Compare;
33 30
34 tmp = count; 31 tmp = count;
35 if (count == compare) 32 if (count == compare)
@@ -52,14 +49,18 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count, @@ -52,14 +49,18 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count,
52 qemu_mod_timer(env->timer, next); 49 qemu_mod_timer(env->timer, next);
53 } 50 }
54 51
55 -void cpu_mips_store_count (CPUState *env, uint32_t value) 52 +static void cpu_mips_update_count (CPUState *env, uint32_t count)
56 { 53 {
57 - cpu_mips_update_count(env, value, env->CP0_Compare); 54 + if (env->CP0_Cause & (1 << CP0Ca_DC))
  55 + return;
  56 +
  57 + cpu_mips_store_count(env, count);
58 } 58 }
59 59
60 void cpu_mips_store_compare (CPUState *env, uint32_t value) 60 void cpu_mips_store_compare (CPUState *env, uint32_t value)
61 { 61 {
62 - cpu_mips_update_count(env, cpu_mips_get_count(env), value); 62 + env->CP0_Compare = value;
  63 + cpu_mips_update_count(env, cpu_mips_get_count(env));
63 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) 64 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
64 env->CP0_Cause &= ~(1 << CP0Ca_TI); 65 env->CP0_Cause &= ~(1 << CP0Ca_TI);
65 cpu_mips_irq_request(env, 7, 0); 66 cpu_mips_irq_request(env, 7, 0);
@@ -75,7 +76,7 @@ static void mips_timer_cb (void *opaque) @@ -75,7 +76,7 @@ static void mips_timer_cb (void *opaque)
75 fprintf(logfile, "%s\n", __func__); 76 fprintf(logfile, "%s\n", __func__);
76 } 77 }
77 #endif 78 #endif
78 - cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); 79 + cpu_mips_update_count(env, cpu_mips_get_count(env));
79 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) 80 if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
80 env->CP0_Cause |= 1 << CP0Ca_TI; 81 env->CP0_Cause |= 1 << CP0Ca_TI;
81 cpu_mips_irq_request(env, 7, 1); 82 cpu_mips_irq_request(env, 7, 1);
@@ -85,6 +86,5 @@ void cpu_mips_clock_init (CPUState *env) @@ -85,6 +86,5 @@ void cpu_mips_clock_init (CPUState *env)
85 { 86 {
86 env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); 87 env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
87 env->CP0_Compare = 0; 88 env->CP0_Compare = 0;
88 - cpu_mips_update_count(env, 1, 0); 89 + cpu_mips_update_count(env, 1);
89 } 90 }
90 -