Commit 3504fe171b62bb0362191e1fd66538ff7c4f4210
1 parent
ab1f142b
16 bit DMA fix (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@572 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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10 additions
and
28 deletions
hw/dma.c
| @@ -136,7 +136,7 @@ static uint32_t read_chan (CPUState *env, uint32_t nport) | @@ -136,7 +136,7 @@ static uint32_t read_chan (CPUState *env, uint32_t nport) | ||
| 136 | return (val >> (ncont + (ff << 3))) & 0xff; | 136 | return (val >> (ncont + (ff << 3))) & 0xff; |
| 137 | } | 137 | } |
| 138 | 138 | ||
| 139 | -static void write_chan (uint32_t nport, int size, uint32_t data) | 139 | +static void write_chan (CPUState *env, uint32_t nport, uint32_t data) |
| 140 | { | 140 | { |
| 141 | int ncont, ichan, nreg; | 141 | int ncont, ichan, nreg; |
| 142 | struct dma_regs *r; | 142 | struct dma_regs *r; |
| @@ -146,28 +146,12 @@ static void write_chan (uint32_t nport, int size, uint32_t data) | @@ -146,28 +146,12 @@ static void write_chan (uint32_t nport, int size, uint32_t data) | ||
| 146 | nreg = (nport >> ncont) & 1; | 146 | nreg = (nport >> ncont) & 1; |
| 147 | r = dma_controllers[ncont].regs + ichan; | 147 | r = dma_controllers[ncont].regs + ichan; |
| 148 | 148 | ||
| 149 | - if (2 == size) { | ||
| 150 | - r->base[nreg] = data; | 149 | + if (getff (ncont)) { |
| 150 | + r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); | ||
| 151 | init_chan (ncont, ichan); | 151 | init_chan (ncont, ichan); |
| 152 | + } else { | ||
| 153 | + r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); | ||
| 152 | } | 154 | } |
| 153 | - else { | ||
| 154 | - if (getff (ncont)) { | ||
| 155 | - r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); | ||
| 156 | - init_chan (ncont, ichan); | ||
| 157 | - } | ||
| 158 | - else { | ||
| 159 | - r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); | ||
| 160 | - } | ||
| 161 | - } | ||
| 162 | -} | ||
| 163 | -static void write_chanb (CPUState *env, uint32_t nport, uint32_t data) | ||
| 164 | -{ | ||
| 165 | - write_chan (nport, 1, data); | ||
| 166 | -} | ||
| 167 | - | ||
| 168 | -static void write_chanw (CPUState *env, uint32_t nport, uint32_t data) | ||
| 169 | -{ | ||
| 170 | - write_chan (nport, 2, data); | ||
| 171 | } | 155 | } |
| 172 | 156 | ||
| 173 | static void write_cont (CPUState *env, uint32_t nport, uint32_t data) | 157 | static void write_cont (CPUState *env, uint32_t nport, uint32_t data) |
| @@ -370,14 +354,12 @@ void DMA_init (void) | @@ -370,14 +354,12 @@ void DMA_init (void) | ||
| 370 | int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; | 354 | int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
| 371 | 355 | ||
| 372 | for (i = 0; i < 8; i++) { | 356 | for (i = 0; i < 8; i++) { |
| 373 | - register_ioport_write (i, 1, write_chanb, 1); | ||
| 374 | - register_ioport_write (i, 1, write_chanw, 2); | 357 | + register_ioport_write (i, 1, write_chan, 1); |
| 375 | 358 | ||
| 376 | - register_ioport_write (0xc0 + (i << 1), 1, write_chanb, 1); | ||
| 377 | - register_ioport_write (0xc0 + (i << 1), 1, write_chanw, 2); | 359 | + register_ioport_write (0xc0 + (i << 1), 1, write_chan, 1); |
| 378 | 360 | ||
| 379 | register_ioport_read (i, 1, read_chan, 1); | 361 | register_ioport_read (i, 1, read_chan, 1); |
| 380 | - register_ioport_read (0xc0 + (i << 1), 1, read_chan, 2); | 362 | + register_ioport_read (0xc0 + (i << 1), 1, read_chan, 1); |
| 381 | } | 363 | } |
| 382 | 364 | ||
| 383 | for (i = 0; i < LENOFA (page_port_list); i++) { | 365 | for (i = 0; i < LENOFA (page_port_list); i++) { |
| @@ -390,6 +372,6 @@ void DMA_init (void) | @@ -390,6 +372,6 @@ void DMA_init (void) | ||
| 390 | register_ioport_write (0xd0 + (i << 1), 1, write_cont, 1); | 372 | register_ioport_write (0xd0 + (i << 1), 1, write_cont, 1); |
| 391 | } | 373 | } |
| 392 | 374 | ||
| 393 | - write_cont (NULL, 0xd, 0); | ||
| 394 | - write_cont (NULL, 0xdd, 0); | 375 | + write_cont (NULL, 0x0d, 0); |
| 376 | + write_cont (NULL, 0xda, 0); | ||
| 395 | } | 377 | } |