initial at91 lcdc implementation

Evgeniy Dushistov
1 parent 5eb9fc83
Showing 4 changed files with 231 additions and 2 deletions
Makefile.target
hw/at91_lcdc.c
hw/at91sam9.c
hw/at91sam9263_defs.h
@@ -411,7 +411,7 @@ obj-sparc-y += cs4231.o eccmemctl.o sbi.o sun4c_intctl.o
 endif
 obj-arm-y = integratorcp.o versatilepb.o smc91c111.o arm_pic.o arm_timer.o
-obj-arm-y += pflash_atmel.o at91sam9.o spi_flash.o
+obj-arm-y += pflash_atmel.o at91sam9.o spi_flash.o at91_lcdc.o
 obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o
 obj-arm-y += versatile_pci.o
 obj-arm-y += realview_gic.o realview.o arm_sysctl.o mpcore.o
+/*
+ * AT91 SAM9 LCD Controller (LCDC)
+ * Written by Evgeniy Dushistov
+ * This code is licenced under the GPL.
+ */
+#include "sysbus.h"
+#include "console.h"
+#include "pixel_ops.h"
+
+#define LCDC_SIZE 0x100000
+
+#define LCDC_DMABADDR1 0x0
+#define LCDC_DMAFRMCFG 0x18
+#define LCDC_DMACON    0x1C
+#define LCDC_LCDCON1   0x800
+#define LCDC_LCDCON2   0x804
+#define LCDC_LCDFRMCFG 0x810
+#define LCDC_PWRCON    0x83C
+
+#define DMACON_DMAEN 1
+
+typedef struct LCDCState {
+    SysBusDevice busdev;
+    qemu_irq irq;
+    DisplayState *ds;
+    uint32_t dmacon;
+    uint32_t pwrcon;
+    uint32_t dmafrmcfg;
+    uint32_t lcdcon1;
+    uint32_t lcdcon2;
+    uint32_t lcdfrmcfg;
+    uint32_t dmabaddr1;
+} LCDCState;
+
+#define AT91_LCDC_DEBUG
+#ifdef AT91_LCDC_DEBUG
+#define DPRINTF(fmt, ...)                           \
+    do {                                            \
+        printf("AT91LCD: " fmt , ## __VA_ARGS__);    \
+    } while (0)
+#else
+#define DPRINTF(fmt, ...) do { } while (0)
+#endif
+
+
+static uint32_t at91_lcdc_mem_read(void *opaque, target_phys_addr_t offset)
+{
+    LCDCState *s = opaque;
+
+    offset &= LCDC_SIZE - 1;
+    DPRINTF("read from %X\n", offset);
+    switch (offset) {
+    case LCDC_PWRCON:
+        return s->pwrcon;
+    case LCDC_DMACON:
+        return s->dmacon;
+    case LCDC_DMAFRMCFG:
+        return s->dmafrmcfg;
+    case LCDC_LCDCON1:
+        return s->lcdcon1;
+    case LCDC_LCDCON2:
+        return s->lcdcon2;
+    case LCDC_LCDFRMCFG:
+        return s->lcdfrmcfg;
+    default:
+        DPRINTF("unsup. read\n");
+        return 0;
+    }
+}
+
+static void at91_lcdc_mem_write(void *opaque, target_phys_addr_t offset,
+                uint32_t value)
+{
+    LCDCState *s = opaque;
+    offset &= LCDC_SIZE - 1;
+    DPRINTF("write to %X: %X\n", offset, value);
+
+    switch (offset) {
+    case LCDC_DMABADDR1:
+        s->dmabaddr1 = value;
+        break;
+    case LCDC_PWRCON:
+        s->pwrcon = value;
+        break;
+    case LCDC_DMACON:
+        s->dmacon = value;
+        break;
+    case LCDC_DMAFRMCFG:
+        s->dmafrmcfg = value;
+        break;
+    case LCDC_LCDCON1:
+        s->lcdcon1 = value;
+        break;
+    case LCDC_LCDCON2:
+        DPRINTF("pixel size %u\n", (value >> 5) & 7);
+        s->lcdcon2 = value;
+        break;
+     case LCDC_LCDFRMCFG:
+        DPRINTF("lineval %u, linsize %u\n", value & 0x7FF, (value >> 21) & 0x7FF);
+        qemu_console_resize(s->ds, ((value >> 21) & 0x7FF) + 1, (value & 0x7FF) + 1);
+        s->lcdfrmcfg = value;
+        break;
+    default:
+        DPRINTF("unsup. write\n");
+    }
+}
+
+static CPUReadMemoryFunc *at91_lcdc_readfn[] = {
+    at91_lcdc_mem_read,
+    at91_lcdc_mem_read,
+    at91_lcdc_mem_read,
+};
+
+static CPUWriteMemoryFunc *at91_lcdc_writefn[] = {
+    at91_lcdc_mem_write,
+    at91_lcdc_mem_write,
+    at91_lcdc_mem_write,
+};
+
+static void at91_lcdc_reset(void *opaque)
+{
+    LCDCState *s = opaque;
+    s->pwrcon = 0x0000000e;
+    s->dmacon = 0;
+    s->dmafrmcfg = 0;
+    s->lcdcon1 = 0x00002000;
+    s->lcdfrmcfg = 0;
+}
+
+struct pixel8 {
+    unsigned b : 2;
+    unsigned g : 3;
+    unsigned r : 3;
+};
+
+union pixel8u {
+    struct pixel8 p;
+    uint8_t val;
+};
+
+static void at91_lcdc_update_display(void *opaque)
+{
+    LCDCState *s = opaque;
+    uint32_t color;
+    int x, y;
+    uint8_t *d;
+    int width = ((s->lcdfrmcfg >> 21) & 0x7FF) + 1;
+    int height = (s->lcdfrmcfg & 0x7FF) + 1;
+    int q_bpp = (ds_get_bits_per_pixel(s->ds) + 7) >> 3;
+    int bpp;
+    int bpp_idx = (s->lcdcon2 >> 5) & 7;
+    union pixel8u tmp;
+
+    DPRINTF("update begin\n");
+    if (!(s->dmacon & DMACON_DMAEN))
+        return;
+    DPRINTF("update continue\n");
+    switch (bpp_idx) {
+    case 0 ... 4:
+        bpp = 1 << bpp_idx;
+        break;
+    case 5 ... 6:
+        bpp = 24;
+        break;
+    default:
+        fprintf(stderr, "Unknown pixel size\n");
+        return;//reserved value, unknown pixel size
+    }
+    /*TODO: fix this restriction*/
+    if (bpp != 8) {
+        fprintf(stderr, "Unsupported pixel size\n");
+        return;
+    }
+    int once = 0;
+    for (y = 0; y < height; ++y) {        
+        for (x = 0; x < width; ++x) {
+            cpu_physical_memory_read(s->dmabaddr1 + width * y + x, &tmp.val, 1);
+            if (tmp.val != 0 && once == 0) {
+                once = 1;
+                DPRINTF("not null %X, %X, %X, bpp %d\n", (unsigned)tmp.p.r << 5, (unsigned)tmp.p.g << 5, (unsigned)tmp.p.b << 6, ds_get_bits_per_pixel(s->ds));
+            }
+            switch (ds_get_bits_per_pixel(s->ds)) {
+            case 8:
+                color = rgb_to_pixel8(tmp.p.r, tmp.p.g, tmp.p.b);
+                break;
+            case 15:
+                color = rgb_to_pixel15(tmp.p.r, tmp.p.g, tmp.p.b);
+                break;
+            case 16:
+                color = rgb_to_pixel16(tmp.p.r, tmp.p.g, tmp.p.b);
+                break;
+            case 24:
+                color = rgb_to_pixel24(tmp.p.r, tmp.p.g, tmp.p.b);
+                break;
+            case 32:
+                color = rgb_to_pixel32((unsigned)tmp.p.r << 5, (unsigned)tmp.p.g << 5, (unsigned)tmp.p.b << 6);
+                break;
+            default:
+                return;
+            }
+
+            d = ds_get_data(s->ds) + ds_get_linesize(s->ds) * y + q_bpp * x;
+            *d = color;
+        }
+    }
+
+    dpy_update(s->ds, 0, 0, width, height);
+}
+
+static void at91_lcdc_init(SysBusDevice *dev)
+{
+    LCDCState *s = FROM_SYSBUS(typeof(*s), dev);
+    int lcdc_regs;
+
+    sysbus_init_irq(dev, &s->irq);
+    lcdc_regs = cpu_register_io_memory(at91_lcdc_readfn,
+                                      at91_lcdc_writefn, s);
+    sysbus_init_mmio(dev, LCDC_SIZE, lcdc_regs);    
+    qemu_register_reset(at91_lcdc_reset, s);
+    s->ds = graphic_console_init(at91_lcdc_update_display, NULL, NULL, NULL, s);
+}
+
+static void at91_lcdc_register(void)
+{
+    sysbus_register_dev("at91,lcdc", sizeof(LCDCState), at91_lcdc_init);
+}
+
+device_init(at91_lcdc_register)
@@ -336,7 +336,7 @@ static void at91sam9_init(ram_addr_t ram_size,
     sysbus_mmio_map(sysbus_from_qdev(dev), 0, AT91_EMAC_BASE);
     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[21]);
-
+    sysbus_create_simple("at91,lcdc", AT91_LCDC_BASE, pic[26]);
     /*
       we use variant of booting from external memory (NOR FLASH),
       it mapped to 0x0 at start, and also it is accessable from 0x10000000 address
@@ -2,6 +2,7 @@
 #define _HW_AT91SAM9263_DEFS_H_
 /* base periph addresses */
+#define AT91_LCDC_BASE        0x00700000
 #define AT91_PERIPH_BASE     0xF0000000
 #define AT91_TC012_BASE      0xFFF7C000
 #define AT91_USART0_BASE     0xFFF8C000