gwj / at91sam9263 · Commits

Commit 3464c5899891efa0b7cb86b5a8090da50a3e6c88

Authored by ths
1 parent 2f062c72

Add INTC controller prototype, by Magnus Damm. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3271 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 51 additions and 0 deletions
hw/sh7750.c
  View file @3464c58
@@ -51,6 +51,14 @@ typedef struct SH7750State { @@ -51,6 +51,14 @@ typedef struct SH7750State {
51 uint16_t periph_pdtrb; /* Imposed by the peripherals */ 51 uint16_t periph_pdtrb; /* Imposed by the peripherals */
52 uint16_t periph_portdirb; /* Direction seen from the peripherals */ 52 uint16_t periph_portdirb; /* Direction seen from the peripherals */
53 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ 53 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
  54 +
  55 + uint16_t icr;
  56 + uint16_t ipra;
  57 + uint16_t iprb;
  58 + uint16_t iprc;
  59 + uint16_t iprd;
  60 + uint32_t intpri00;
  61 + uint32_t intmsk00;
54 /* Cache */ 62 /* Cache */
55 uint32_t ccr; 63 uint32_t ccr;
56 64
@@ -207,6 +215,16 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr) @@ -207,6 +215,16 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
207 return porta_lines(s); 215 return porta_lines(s);
208 case SH7750_PDTRB_A7: 216 case SH7750_PDTRB_A7:
209 return portb_lines(s); 217 return portb_lines(s);
  218 + case 0x1fd00000:
  219 + return s->icr;
  220 + case 0x1fd00004:
  221 + return s->ipra;
  222 + case 0x1fd00008:
  223 + return s->iprb;
  224 + case 0x1fd0000c:
  225 + return s->iprc;
  226 + case 0x1fd00010:
  227 + return s->iprd;
210 default: 228 default:
211 error_access("word read", addr); 229 error_access("word read", addr);
212 assert(0); 230 assert(0);
@@ -242,6 +260,14 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr) @@ -242,6 +260,14 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
242 return 0x00110000; /* Minimum caches */ 260 return 0x00110000; /* Minimum caches */
243 case 0x1f000044: /* Processor version PRR */ 261 case 0x1f000044: /* Processor version PRR */
244 return 0x00000100; /* SH7750R */ 262 return 0x00000100; /* SH7750R */
  263 + case 0x1e080000:
  264 + return s->intpri00;
  265 + case 0x1e080020:
  266 + return 0;
  267 + case 0x1e080040:
  268 + return s->intmsk00;
  269 + case 0x1e080060:
  270 + return 0;
245 default: 271 default:
246 error_access("long read", addr); 272 error_access("long read", addr);
247 assert(0); 273 assert(0);
@@ -300,6 +326,21 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, @@ -300,6 +326,21 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
300 assert(0); 326 assert(0);
301 } 327 }
302 return; 328 return;
  329 + case 0x1fd00000:
  330 + s->icr = mem_value;
  331 + return;
  332 + case 0x1fd00004:
  333 + s->ipra = mem_value;
  334 + return;
  335 + case 0x1fd00008:
  336 + s->iprb = mem_value;
  337 + return;
  338 + case 0x1fd0000c:
  339 + s->iprc = mem_value;
  340 + return;
  341 + case 0x1fd00010:
  342 + s->iprd = mem_value;
  343 + return;
303 default: 344 default:
304 error_access("word write", addr); 345 error_access("word write", addr);
305 assert(0); 346 assert(0);
@@ -364,6 +405,16 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, @@ -364,6 +405,16 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
364 case SH7750_CCR_A7: 405 case SH7750_CCR_A7:
365 s->ccr = mem_value; 406 s->ccr = mem_value;
366 return; 407 return;
  408 + case 0x1e080000:
  409 + s->intpri00 = mem_value;
  410 + return;
  411 + case 0x1e080020:
  412 + return;
  413 + case 0x1e080040:
  414 + s->intmsk00 = mem_value;
  415 + return;
  416 + case 0x1e080060:
  417 + return;
367 default: 418 default:
368 error_access("long write", addr); 419 error_access("long write", addr);
369 assert(0); 420 assert(0);