gwj / at91sam9263 · Commits

Commit 33093a0afc069cc505e35b2580260faad4a6ecd4

Authored by aurel32
1 parent 0c34a5d7

Parallel port reset 

Attached patch adds a reset handler to parallel port, so it gets correct
register values after a reset.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5942 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 11 additions and 5 deletions
hw/parallel.c
  View file @33093a0
@@ -418,8 +418,10 @@ static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) @@ -418,8 +418,10 @@ static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
418 return ret; 418 return ret;
419 } 419 }
420 420
421 -static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr) 421 +static void parallel_reset(void *opaque)
422 { 422 {
  423 + ParallelState *s = opaque;
  424 +
423 s->datar = ~0; 425 s->datar = ~0;
424 s->dataw = ~0; 426 s->dataw = ~0;
425 s->status = PARA_STS_BUSY; 427 s->status = PARA_STS_BUSY;
@@ -430,9 +432,7 @@ static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr) @@ -430,9 +432,7 @@ static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
430 s->control = PARA_CTR_SELECT; 432 s->control = PARA_CTR_SELECT;
431 s->control |= PARA_CTR_INIT; 433 s->control |= PARA_CTR_INIT;
432 s->control |= 0xc0; 434 s->control |= 0xc0;
433 - s->irq = irq;  
434 s->irq_pending = 0; 435 s->irq_pending = 0;
435 - s->chr = chr;  
436 s->hw_driver = 0; 436 s->hw_driver = 0;
437 s->epp_timeout = 0; 437 s->epp_timeout = 0;
438 s->last_read_offset = ~0U; 438 s->last_read_offset = ~0U;
@@ -447,7 +447,10 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr) @@ -447,7 +447,10 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
447 s = qemu_mallocz(sizeof(ParallelState)); 447 s = qemu_mallocz(sizeof(ParallelState));
448 if (!s) 448 if (!s)
449 return NULL; 449 return NULL;
450 - parallel_reset(s, irq, chr); 450 + s->irq = irq;
  451 + s->chr = chr;
  452 + parallel_reset(s);
  453 + qemu_register_reset(parallel_reset, s);
451 454
452 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { 455 if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
453 s->hw_driver = 1; 456 s->hw_driver = 1;
@@ -538,8 +541,11 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq @@ -538,8 +541,11 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
538 s = qemu_mallocz(sizeof(ParallelState)); 541 s = qemu_mallocz(sizeof(ParallelState));
539 if (!s) 542 if (!s)
540 return NULL; 543 return NULL;
541 - parallel_reset(s, irq, chr); 544 + s->irq = irq;
  545 + s->chr = chr;
542 s->it_shift = it_shift; 546 s->it_shift = it_shift;
  547 + parallel_reset(s);
  548 + qemu_register_reset(parallel_reset, s);
543 549
544 io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s); 550 io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
545 cpu_register_physical_memory(base, 8 << it_shift, io_sw); 551 cpu_register_physical_memory(base, 8 << it_shift, io_sw);