gwj / at91sam9263 · Commits

Commit 3299908c834fd1699f59638dd36eba187963a694

Authored by blueswir1
1 parent d2889a3e

Fix Sparc64 wrfprs, move VIS ops where they belong, more VIS ops 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2656 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 2 changed files with 111 additions and 38 deletions
target-sparc/op.c
  View file @3299908
... ... @@ -1864,4 +1864,24 @@ void OPPROTO op_faligndata()
1864 1864 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
1865 1865 (*((uint64_t *)&DT0)) = tmp;
1866 1866 }
  1867 +
  1868 +void OPPROTO op_movl_FT0_0(void)
  1869 +{
  1870 + (*((uint32_t *)&FT0)) = 0;
  1871 +}
  1872 +
  1873 +void OPPROTO op_movl_DT0_0(void)
  1874 +{
  1875 + (*((uint64_t *)&DT0)) = 0;
  1876 +}
  1877 +
  1878 +void OPPROTO op_movl_FT0_1(void)
  1879 +{
  1880 + (*((uint32_t *)&FT0)) = 0xffffffff;
  1881 +}
  1882 +
  1883 +void OPPROTO op_movl_DT0_1(void)
  1884 +{
  1885 + (*((uint64_t *)&DT0)) = 0xffffffffffffffffULL;
  1886 +}
1867 1887 #endif
... ...
target-sparc/translate.c
  View file @3299908
... ... @@ -1931,7 +1931,13 @@ static void disas_sparc_insn(DisasContext * dc)
1931 1931 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1932 1932 break;
1933 1933 case 0x6: /* V9 wrfprs */
  1934 + gen_op_xor_T1_T0();
1934 1935 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
  1936 + save_state(dc);
  1937 + gen_op_next_insn();
  1938 + gen_op_movl_T0_0();
  1939 + gen_op_exit_tb();
  1940 + dc->is_br = 1;
1935 1941 break;
1936 1942 case 0xf: /* V9 sir, nop if user */
1937 1943 #if !defined(CONFIG_USER_ONLY)
... ... @@ -2148,47 +2154,94 @@ static void disas_sparc_insn(DisasContext * dc)
2148 2154 gen_movl_T0_reg(rd);
2149 2155 break;
2150 2156 }
2151   - case 0x36: /* UltraSparc shutdown, VIS */
2152   - {
2153   - int opf = GET_FIELD_SP(insn, 5, 13);
2154   - rs1 = GET_FIELD(insn, 13, 17);
2155   - rs2 = GET_FIELD(insn, 27, 31);
2156   -
2157   - switch (opf) {
2158   - case 0x018: /* VIS I alignaddr */
2159   - if (gen_trap_ifnofpu(dc))
2160   - goto jmp_insn;
2161   - gen_movl_reg_T0(rs1);
2162   - gen_movl_reg_T1(rs2);
2163   - gen_op_alignaddr();
2164   - gen_movl_T0_reg(rd);
2165   - break;
2166   - case 0x01a: /* VIS I alignaddrl */
2167   - if (gen_trap_ifnofpu(dc))
2168   - goto jmp_insn;
2169   - // XXX
2170   - break;
2171   - case 0x048: /* VIS I faligndata */
2172   - if (gen_trap_ifnofpu(dc))
2173   - goto jmp_insn;
2174   - gen_op_load_fpr_DT0(rs1);
2175   - gen_op_load_fpr_DT1(rs2);
2176   - gen_op_faligndata();
2177   - gen_op_store_DT0_fpr(rd);
2178   - break;
2179   - default:
2180   - goto illegal_insn;
2181   - }
2182   - break;
2183   - }
2184 2157 #endif
2185 2158 default:
2186 2159 goto illegal_insn;
2187 2160 }
2188 2161 }
2189   - } else if (xop == 0x36 || xop == 0x37) { /* CPop1 & CPop2,
2190   - V9 impdep1 &
2191   - impdep2 */
  2162 + } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
  2163 +#ifdef TARGET_SPARC64
  2164 + int opf = GET_FIELD_SP(insn, 5, 13);
  2165 + rs1 = GET_FIELD(insn, 13, 17);
  2166 + rs2 = GET_FIELD(insn, 27, 31);
  2167 +
  2168 + switch (opf) {
  2169 + case 0x018: /* VIS I alignaddr */
  2170 + if (gen_trap_ifnofpu(dc))
  2171 + goto jmp_insn;
  2172 + gen_movl_reg_T0(rs1);
  2173 + gen_movl_reg_T1(rs2);
  2174 + gen_op_alignaddr();
  2175 + gen_movl_T0_reg(rd);
  2176 + break;
  2177 + case 0x01a: /* VIS I alignaddrl */
  2178 + if (gen_trap_ifnofpu(dc))
  2179 + goto jmp_insn;
  2180 + // XXX
  2181 + break;
  2182 + case 0x048: /* VIS I faligndata */
  2183 + if (gen_trap_ifnofpu(dc))
  2184 + goto jmp_insn;
  2185 + gen_op_load_fpr_DT0(rs1);
  2186 + gen_op_load_fpr_DT1(rs2);
  2187 + gen_op_faligndata();
  2188 + gen_op_store_DT0_fpr(rd);
  2189 + break;
  2190 + case 0x060: /* VIS I fzero */
  2191 + if (gen_trap_ifnofpu(dc))
  2192 + goto jmp_insn;
  2193 + gen_op_movl_DT0_0();
  2194 + gen_op_store_DT0_fpr(rd);
  2195 + break;
  2196 + case 0x061: /* VIS I fzeros */
  2197 + if (gen_trap_ifnofpu(dc))
  2198 + goto jmp_insn;
  2199 + gen_op_movl_FT0_0();
  2200 + gen_op_store_FT0_fpr(rd);
  2201 + break;
  2202 + case 0x074: /* VIS I fsrc1 */
  2203 + if (gen_trap_ifnofpu(dc))
  2204 + goto jmp_insn;
  2205 + gen_op_load_fpr_DT0(rs1);
  2206 + gen_op_store_DT0_fpr(rd);
  2207 + break;
  2208 + case 0x075: /* VIS I fsrc1s */
  2209 + if (gen_trap_ifnofpu(dc))
  2210 + goto jmp_insn;
  2211 + gen_op_load_fpr_FT0(rs1);
  2212 + gen_op_store_FT0_fpr(rd);
  2213 + break;
  2214 + case 0x078: /* VIS I fsrc2 */
  2215 + if (gen_trap_ifnofpu(dc))
  2216 + goto jmp_insn;
  2217 + gen_op_load_fpr_DT0(rs2);
  2218 + gen_op_store_DT0_fpr(rd);
  2219 + break;
  2220 + case 0x079: /* VIS I fsrc2s */
  2221 + if (gen_trap_ifnofpu(dc))
  2222 + goto jmp_insn;
  2223 + gen_op_load_fpr_FT0(rs2);
  2224 + gen_op_store_FT0_fpr(rd);
  2225 + break;
  2226 + case 0x07e: /* VIS I fone */
  2227 + if (gen_trap_ifnofpu(dc))
  2228 + goto jmp_insn;
  2229 + gen_op_movl_DT0_1();
  2230 + gen_op_store_DT0_fpr(rd);
  2231 + break;
  2232 + case 0x07f: /* VIS I fones */
  2233 + if (gen_trap_ifnofpu(dc))
  2234 + goto jmp_insn;
  2235 + gen_op_movl_FT0_1();
  2236 + gen_op_store_FT0_fpr(rd);
  2237 + break;
  2238 + default:
  2239 + goto illegal_insn;
  2240 + }
  2241 +#else
  2242 + goto ncp_insn;
  2243 +#endif
  2244 + } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2192 2245 #ifdef TARGET_SPARC64
2193 2246 goto illegal_insn;
2194 2247 #else
... ... @@ -2995,8 +3048,8 @@ void cpu_dump_state(CPUState *env, FILE *f,
2995 3048 cpu_fprintf(f, "\n");
2996 3049 }
2997 3050 #ifdef TARGET_SPARC64
2998   - cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d\n",
2999   - env->pstate, GET_CCR(env), env->asi, env->tl);
  3051 + cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
  3052 + env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3000 3053 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3001 3054 env->cansave, env->canrestore, env->otherwin, env->wstate,
3002 3055 env->cleanwin, NWINDOWS - 1 - env->cwp);
... ...