gwj / at91sam9263 · Commits

Commit 3157a0a93b65aac3113ba1338221c262663ebd50

Authored by edgar_igl
1 parent 87e92502

More TCG conversions for CRIS. 

* Bit swap insn (bitwise not, endian swap and bit reverse).
* Muls and mulu.
* Extended arithmetics.
* Parts of the condition code handling.
* Use tcg_const_tl.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4069 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 259 additions and 73 deletions
target-cris/translate.c
  View file @3157a0a
... ... @@ -153,9 +153,9 @@ int preg_sizes[] = {
153 153 };
154 154  
155 155 #define t_gen_mov_TN_env(tn, member) \
156   - _t_gen_mov_TN_env((tn), offsetof(CPUState, (member)))
  156 + _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
157 157 #define t_gen_mov_env_TN(member, tn) \
158   - _t_gen_mov_env_TN(offsetof(CPUState, (member)), (tn))
  158 + _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
159 159  
160 160 #define t_gen_mov_TN_reg(tn, regno) \
161 161 _t_gen_mov_TN_env((tn), offsetof(CPUState, regs[regno]))
... ... @@ -174,9 +174,9 @@ static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
174 174 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
175 175 {
176 176 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
177   - tcg_gen_mov_tl(tn, tcg_const_i32(0));
  177 + tcg_gen_mov_tl(tn, tcg_const_tl(0));
178 178 else if (r == PR_VR)
179   - tcg_gen_mov_tl(tn, tcg_const_i32(32));
  179 + tcg_gen_mov_tl(tn, tcg_const_tl(32));
180 180 else
181 181 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, pregs[r]));
182 182 }
... ... @@ -200,7 +200,7 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
200 200 l1 = gen_new_label();
201 201 /* Speculative shift. */
202 202 tcg_gen_shl_tl(d, a, b);
203   - tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
  203 + tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
204 204 /* Clear dst if shift operands were to large. */
205 205 tcg_gen_movi_tl(d, 0);
206 206 gen_set_label(l1);
... ... @@ -213,7 +213,7 @@ static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
213 213 l1 = gen_new_label();
214 214 /* Speculative shift. */
215 215 tcg_gen_shr_tl(d, a, b);
216   - tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
  216 + tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
217 217 /* Clear dst if shift operands were to large. */
218 218 tcg_gen_movi_tl(d, 0);
219 219 gen_set_label(l1);
... ... @@ -226,14 +226,174 @@ static void t_gen_asr(TCGv d, TCGv a, TCGv b)
226 226 l1 = gen_new_label();
227 227 /* Speculative shift. */
228 228 tcg_gen_sar_tl(d, a, b);
229   - tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
  229 + tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
230 230 /* Clear dst if shift operands were to large. */
231 231 tcg_gen_movi_tl(d, 0);
232   - tcg_gen_brcond_tl(TCG_COND_LT, b, tcg_const_i32(0x80000000), l1);
  232 + tcg_gen_brcond_tl(TCG_COND_LT, b, tcg_const_tl(0x80000000), l1);
233 233 tcg_gen_movi_tl(d, 0xffffffff);
234 234 gen_set_label(l1);
235 235 }
236 236  
  237 +/* 64-bit signed mul, lower result in d and upper in d2. */
  238 +static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
  239 +{
  240 + TCGv t0, t1;
  241 +
  242 + t0 = tcg_temp_new(TCG_TYPE_I64);
  243 + t1 = tcg_temp_new(TCG_TYPE_I64);
  244 +
  245 + tcg_gen_ext32s_i64(t0, a);
  246 + tcg_gen_ext32s_i64(t1, b);
  247 + tcg_gen_mul_i64(t0, t0, t1);
  248 +
  249 + tcg_gen_trunc_i64_i32(d, t0);
  250 + tcg_gen_shri_i64(t0, t0, 32);
  251 + tcg_gen_trunc_i64_i32(d2, t0);
  252 +}
  253 +
  254 +/* 64-bit unsigned muls, lower result in d and upper in d2. */
  255 +static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
  256 +{
  257 + TCGv t0, t1;
  258 +
  259 + t0 = tcg_temp_new(TCG_TYPE_I64);
  260 + t1 = tcg_temp_new(TCG_TYPE_I64);
  261 +
  262 + tcg_gen_extu_i32_i64(t0, a);
  263 + tcg_gen_extu_i32_i64(t1, b);
  264 + tcg_gen_mul_i64(t0, t0, t1);
  265 +
  266 + tcg_gen_trunc_i64_i32(d, t0);
  267 + tcg_gen_shri_i64(t0, t0, 32);
  268 + tcg_gen_trunc_i64_i32(d2, t0);
  269 +}
  270 +
  271 +/* Extended arithmetics on CRIS. */
  272 +static inline void t_gen_add_flag(TCGv d, int flag)
  273 +{
  274 + TCGv c;
  275 +
  276 + c = tcg_temp_new(TCG_TYPE_TL);
  277 + t_gen_mov_TN_preg(c, PR_CCS);
  278 + /* Propagate carry into d. */
  279 + tcg_gen_andi_tl(c, c, 1 << flag);
  280 + if (flag)
  281 + tcg_gen_shri_tl(c, c, flag);
  282 + tcg_gen_add_tl(d, d, c);
  283 +}
  284 +
  285 +static inline void t_gen_addx_carry(TCGv d)
  286 +{
  287 + TCGv x, c;
  288 +
  289 + x = tcg_temp_new(TCG_TYPE_TL);
  290 + c = tcg_temp_new(TCG_TYPE_TL);
  291 + t_gen_mov_TN_preg(x, PR_CCS);
  292 + tcg_gen_mov_tl(c, x);
  293 +
  294 + /* Propagate carry into d if X is set. Branch free. */
  295 + tcg_gen_andi_tl(c, c, C_FLAG);
  296 + tcg_gen_andi_tl(x, x, X_FLAG);
  297 + tcg_gen_shri_tl(x, x, 4);
  298 +
  299 + tcg_gen_and_tl(x, x, c);
  300 + tcg_gen_add_tl(d, d, x);
  301 +}
  302 +
  303 +static inline void t_gen_subx_carry(TCGv d)
  304 +{
  305 + TCGv x, c;
  306 +
  307 + x = tcg_temp_new(TCG_TYPE_TL);
  308 + c = tcg_temp_new(TCG_TYPE_TL);
  309 + t_gen_mov_TN_preg(x, PR_CCS);
  310 + tcg_gen_mov_tl(c, x);
  311 +
  312 + /* Propagate carry into d if X is set. Branch free. */
  313 + tcg_gen_andi_tl(c, c, C_FLAG);
  314 + tcg_gen_andi_tl(x, x, X_FLAG);
  315 + tcg_gen_shri_tl(x, x, 4);
  316 +
  317 + tcg_gen_and_tl(x, x, c);
  318 + tcg_gen_sub_tl(d, d, x);
  319 +}
  320 +
  321 +/* Swap the two bytes within each half word of the s operand.
  322 + T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
  323 +static inline void t_gen_swapb(TCGv d, TCGv s)
  324 +{
  325 + TCGv t, org_s;
  326 +
  327 + t = tcg_temp_new(TCG_TYPE_TL);
  328 + org_s = tcg_temp_new(TCG_TYPE_TL);
  329 +
  330 + /* d and s may refer to the same object. */
  331 + tcg_gen_mov_tl(org_s, s);
  332 + tcg_gen_shli_tl(t, org_s, 8);
  333 + tcg_gen_andi_tl(d, t, 0xff00ff00);
  334 + tcg_gen_shri_tl(t, org_s, 8);
  335 + tcg_gen_andi_tl(t, t, 0x00ff00ff);
  336 + tcg_gen_or_tl(d, d, t);
  337 +}
  338 +
  339 +/* Swap the halfwords of the s operand. */
  340 +static inline void t_gen_swapw(TCGv d, TCGv s)
  341 +{
  342 + TCGv t;
  343 + /* d and s refer the same object. */
  344 + t = tcg_temp_new(TCG_TYPE_TL);
  345 + tcg_gen_mov_tl(t, s);
  346 + tcg_gen_shli_tl(d, t, 16);
  347 + tcg_gen_shri_tl(t, t, 16);
  348 + tcg_gen_or_tl(d, d, t);
  349 +}
  350 +
  351 +/* Reverse the within each byte.
  352 + T0 = (((T0 << 7) & 0x80808080) |
  353 + ((T0 << 5) & 0x40404040) |
  354 + ((T0 << 3) & 0x20202020) |
  355 + ((T0 << 1) & 0x10101010) |
  356 + ((T0 >> 1) & 0x08080808) |
  357 + ((T0 >> 3) & 0x04040404) |
  358 + ((T0 >> 5) & 0x02020202) |
  359 + ((T0 >> 7) & 0x01010101));
  360 + */
  361 +static inline void t_gen_swapr(TCGv d, TCGv s)
  362 +{
  363 + struct {
  364 + int shift; /* LSL when positive, LSR when negative. */
  365 + uint32_t mask;
  366 + } bitrev [] = {
  367 + {7, 0x80808080},
  368 + {5, 0x40404040},
  369 + {3, 0x20202020},
  370 + {1, 0x10101010},
  371 + {-1, 0x08080808},
  372 + {-3, 0x04040404},
  373 + {-5, 0x02020202},
  374 + {-7, 0x01010101}
  375 + };
  376 + int i;
  377 + TCGv t, org_s;
  378 +
  379 + /* d and s refer the same object. */
  380 + t = tcg_temp_new(TCG_TYPE_TL);
  381 + org_s = tcg_temp_new(TCG_TYPE_TL);
  382 + tcg_gen_mov_tl(org_s, s);
  383 +
  384 + tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
  385 + tcg_gen_andi_tl(d, t, bitrev[0].mask);
  386 + for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
  387 + if (bitrev[i].shift >= 0) {
  388 + tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
  389 + } else {
  390 + tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
  391 + }
  392 + tcg_gen_andi_tl(t, t, bitrev[i].mask);
  393 + tcg_gen_or_tl(d, d, t);
  394 + }
  395 +}
  396 +
237 397 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
238 398 {
239 399 TranslationBlock *tb;
... ... @@ -241,10 +401,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
241 401 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
242 402 tcg_gen_goto_tb(n);
243 403 tcg_gen_movi_tl(cpu_T[0], dest);
244   - gen_op_movl_pc_T0();
  404 + t_gen_mov_env_TN(pc, cpu_T[0]);
245 405 tcg_gen_exit_tb((long)tb + n);
246 406 } else {
247   - gen_op_movl_pc_T0();
  407 + t_gen_mov_env_TN(pc, cpu_T[0]);
248 408 tcg_gen_exit_tb(0);
249 409 }
250 410 }
... ... @@ -264,13 +424,9 @@ static int sign_extend(unsigned int val, unsigned int width)
264 424  
265 425 static inline void cris_clear_x_flag(DisasContext *dc)
266 426 {
267   - TCGv ccs;
268   -
269   - ccs = tcg_temp_new(TCG_TYPE_TL);
270   -
271   - t_gen_mov_TN_preg(ccs, PR_CCS);
272   - tcg_gen_andi_i32(ccs, ccs, ~X_FLAG);
273   - t_gen_mov_preg_TN(PR_CCS, ccs);
  427 + t_gen_mov_TN_preg(cpu_T[0], PR_CCS);
  428 + tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ~X_FLAG);
  429 + t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
274 430 dc->flagx_live = 1;
275 431 dc->flags_x = 0;
276 432 }
... ... @@ -339,7 +495,7 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
339 495 if (mask == 0)
340 496 dc->update_cc = 0;
341 497 else {
342   - gen_op_update_cc_mask(mask);
  498 + t_gen_mov_env_TN(cc_mask, tcg_const_tl(mask));
343 499 dc->flags_live = 0;
344 500 }
345 501 }
... ... @@ -347,13 +503,13 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
347 503 static void cris_update_cc_op(DisasContext *dc, int op)
348 504 {
349 505 dc->cc_op = op;
350   - gen_op_update_cc_op(op);
351 506 dc->flags_live = 0;
  507 + t_gen_mov_env_TN(cc_op, tcg_const_tl(op));
352 508 }
353 509 static void cris_update_cc_size(DisasContext *dc, int size)
354 510 {
355 511 dc->cc_size = size;
356   - gen_op_update_cc_size_im(size);
  512 + t_gen_mov_env_TN(cc_size, tcg_const_tl(size));
357 513 }
358 514  
359 515 /* op is the operation.
... ... @@ -364,10 +520,15 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
364 520 {
365 521 int writeback = 1;
366 522 if (dc->update_cc) {
  523 +
367 524 cris_update_cc_op(dc, op);
368 525 cris_update_cc_size(dc, size);
369   - gen_op_update_cc_x(dc->flagx_live, dc->flags_x);
370   - gen_op_update_cc_dest_T0();
  526 + t_gen_mov_env_TN(cc_dest, cpu_T[0]);
  527 +
  528 + /* FIXME: This shouldn't be needed. But we don't pass the
  529 + tests without it. Investigate. */
  530 + t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
  531 + t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
371 532 }
372 533  
373 534 /* Emit the ALU insns. */
... ... @@ -376,25 +537,25 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
376 537 case CC_OP_ADD:
377 538 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
378 539 /* Extended arithmetics. */
379   - gen_op_addxl_T0_C();
  540 + t_gen_addx_carry(cpu_T[0]);
380 541 break;
381 542 case CC_OP_ADDC:
382 543 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
383   - gen_op_addl_T0_C();
  544 + t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
384 545 break;
385 546 case CC_OP_MCP:
386 547 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
387   - gen_op_addl_T0_R();
  548 + t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
388 549 break;
389 550 case CC_OP_SUB:
390   - tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
  551 + tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
391 552 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  553 + tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
392 554 /* CRIS flag evaluation needs ~src. */
393   - tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
394   - gen_op_not_T1_T1();
  555 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
395 556  
396 557 /* Extended arithmetics. */
397   - gen_op_subxl_T0_C();
  558 + t_gen_subx_carry(cpu_T[0]);
398 559 break;
399 560 case CC_OP_MOVE:
400 561 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
... ... @@ -418,11 +579,11 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
418 579 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
419 580 break;
420 581 case CC_OP_NEG:
421   - /* TCG-FIXME: this is not optimal. Many archs have
422   - fast neg insns. */
423   - tcg_gen_sub_tl(cpu_T[0], tcg_const_i32(0), cpu_T[1]);
  582 + /* Hopefully the TCG backend recognizes this pattern
  583 + and makes a real neg out of it. */
  584 + tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
424 585 /* Extended arithmetics. */
425   - gen_op_subxl_T0_C();
  586 + t_gen_subx_carry(cpu_T[0]);
426 587 break;
427 588 case CC_OP_LZ:
428 589 gen_op_lz_T0_T1();
... ... @@ -432,27 +593,44 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
432 593 writeback = 0;
433 594 break;
434 595 case CC_OP_MULS:
435   - gen_op_muls_T0_T1();
436   - break;
  596 + {
  597 + TCGv mof;
  598 + mof = tcg_temp_new(TCG_TYPE_TL);
  599 + t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
  600 + t_gen_mov_preg_TN(PR_MOF, mof);
  601 + }
  602 + break;
437 603 case CC_OP_MULU:
438   - gen_op_mulu_T0_T1();
439   - break;
  604 + {
  605 + TCGv mof;
  606 + mof = tcg_temp_new(TCG_TYPE_TL);
  607 + t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
  608 + t_gen_mov_preg_TN(PR_MOF, mof);
  609 + }
  610 + break;
440 611 case CC_OP_DSTEP:
441 612 gen_op_dstep_T0_T1();
442 613 break;
443 614 case CC_OP_BOUND:
444   - gen_op_bound_T0_T1();
445   - break;
  615 + {
  616 + int l1;
  617 + l1 = gen_new_label();
  618 + tcg_gen_brcond_tl(TCG_COND_LEU,
  619 + cpu_T[0], cpu_T[1], l1);
  620 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  621 + gen_set_label(l1);
  622 + }
  623 + break;
446 624 case CC_OP_CMP:
447   - tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
  625 + tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
448 626 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
449 627 /* CRIS flag evaluation needs ~src. */
450   - tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
  628 + tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
451 629 /* CRIS flag evaluation needs ~src. */
452   - gen_op_not_T1_T1();
  630 + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
453 631  
454 632 /* Extended arithmetics. */
455   - gen_op_subxl_T0_C();
  633 + t_gen_subx_carry(cpu_T[0]);
456 634 writeback = 0;
457 635 break;
458 636 default:
... ... @@ -462,7 +640,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
462 640 }
463 641  
464 642 if (dc->update_cc)
465   - gen_op_update_cc_src_T1();
  643 + t_gen_mov_env_TN(cc_src, cpu_T[1]);
466 644  
467 645 if (size == 1)
468 646 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
... ... @@ -486,7 +664,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
486 664 }
487 665 }
488 666 if (dc->update_cc)
489   - gen_op_update_cc_result_T0();
  667 + t_gen_mov_env_TN(cc_result, cpu_T[0]);
490 668  
491 669 {
492 670 /* TODO: Optimize this. */
... ... @@ -617,8 +795,8 @@ static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
617 795 gen_tst_cc (dc, cond);
618 796 gen_op_evaluate_bcc ();
619 797 }
620   - gen_op_movl_T0_im (dc->delayed_pc);
621   - gen_op_movl_btarget_T0 ();
  798 + tcg_gen_movi_tl(cpu_T[0], dc->delayed_pc);
  799 + t_gen_mov_env_TN(btarget, cpu_T[0]);
622 800 }
623 801  
624 802 /* Dynamic jumps, when the dest is in a live reg for example. */
... ... @@ -726,7 +904,7 @@ static void do_postinc (DisasContext *dc, int size)
726 904 if (!dc->postinc)
727 905 return;
728 906 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
729   - gen_op_addl_T0_im(size);
  907 + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], size);
730 908 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
731 909 }
732 910  
... ... @@ -874,7 +1052,7 @@ static unsigned int dec_moveq(DisasContext *dc)
874 1052 imm = sign_extend(dc->op1, 5);
875 1053 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
876 1054  
877   - t_gen_mov_reg_TN(dc->op2, tcg_const_i32(imm));
  1055 + t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
878 1056 if (!dc->flagx_live || dc->flags_x)
879 1057 cris_clear_x_flag(dc);
880 1058 return 2;
... ... @@ -940,7 +1118,7 @@ static unsigned int dec_btstq(DisasContext *dc)
940 1118 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
941 1119  
942 1120 cris_update_cc_op(dc, CC_OP_FLAGS);
943   - gen_op_movl_flags_T0();
  1121 + t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
944 1122 dc->flags_live = 1;
945 1123 return 2;
946 1124 }
... ... @@ -1000,10 +1178,10 @@ static unsigned int dec_scc_r(DisasContext *dc)
1000 1178 if (cond != CC_A)
1001 1179 {
1002 1180 gen_tst_cc (dc, cond);
1003   - gen_op_movl_T1_T0();
  1181 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1004 1182 }
1005 1183 else
1006   - gen_op_movl_T1_im(1);
  1184 + tcg_gen_movi_tl(cpu_T[1], 1);
1007 1185  
1008 1186 cris_cc_mask(dc, 0);
1009 1187 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
... ... @@ -1147,11 +1325,18 @@ static unsigned int dec_cmp_r(DisasContext *dc)
1147 1325  
1148 1326 static unsigned int dec_abs_r(DisasContext *dc)
1149 1327 {
  1328 + int l1;
  1329 +
1150 1330 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1151 1331 dc->op1, dc->op2));
1152 1332 cris_cc_mask(dc, CC_MASK_NZ);
1153 1333 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
1154   - gen_op_absl_T1_T1();
  1334 +
  1335 + /* TODO: consider a branch free approach. */
  1336 + l1 = gen_new_label();
  1337 + tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
  1338 + tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
  1339 + gen_set_label(l1);
1155 1340 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1156 1341 return 2;
1157 1342 }
... ... @@ -1215,14 +1400,14 @@ static unsigned int dec_swap_r(DisasContext *dc)
1215 1400 cris_cc_mask(dc, CC_MASK_NZ);
1216 1401 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1217 1402 if (dc->op2 & 8)
1218   - gen_op_not_T0_T0();
  1403 + tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
1219 1404 if (dc->op2 & 4)
1220   - gen_op_swapw_T0_T0();
  1405 + t_gen_swapw(cpu_T[0], cpu_T[0]);
1221 1406 if (dc->op2 & 2)
1222   - gen_op_swapb_T0_T0();
  1407 + t_gen_swapb(cpu_T[0], cpu_T[0]);
1223 1408 if (dc->op2 & 1)
1224   - gen_op_swapr_T0_T0();
1225   - gen_op_movl_T1_T0();
  1409 + t_gen_swapr(cpu_T[0], cpu_T[0]);
  1410 + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1226 1411 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1227 1412 return 2;
1228 1413 }
... ... @@ -1244,7 +1429,7 @@ static unsigned int dec_addi_r(DisasContext *dc)
1244 1429 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1245 1430 cris_cc_mask(dc, 0);
1246 1431 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1247   - t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_i32(dc->zzsize));
  1432 + t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1248 1433 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1249 1434 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1250 1435 return 2;
... ... @@ -1256,7 +1441,7 @@ static unsigned int dec_addi_acr(DisasContext *dc)
1256 1441 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1257 1442 cris_cc_mask(dc, 0);
1258 1443 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1259   - t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_i32(dc->zzsize));
  1444 + t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1260 1445  
1261 1446 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1262 1447 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
... ... @@ -1283,7 +1468,7 @@ static unsigned int dec_btst_r(DisasContext *dc)
1283 1468 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1284 1469  
1285 1470 cris_update_cc_op(dc, CC_OP_FLAGS);
1286   - gen_op_movl_flags_T0();
  1471 + t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1287 1472 dc->flags_live = 1;
1288 1473 return 2;
1289 1474 }
... ... @@ -1910,7 +2095,7 @@ static unsigned int dec_lapc_im(DisasContext *dc)
1910 2095 cris_cc_mask(dc, 0);
1911 2096 imm = ldl_code(dc->pc + 2);
1912 2097 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
1913   - t_gen_mov_reg_TN(rd, tcg_const_i32(dc->pc + imm));
  2098 + t_gen_mov_reg_TN(rd, tcg_const_tl(dc->pc + imm));
1914 2099 return 6;
1915 2100 }
1916 2101  
... ... @@ -1921,7 +2106,7 @@ static unsigned int dec_jump_p(DisasContext *dc)
1921 2106 cris_cc_mask(dc, 0);
1922 2107 /* Store the return address in Pd. */
1923 2108 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
1924   - gen_op_movl_btarget_T0();
  2109 + t_gen_mov_env_TN(btarget, cpu_T[0]);
1925 2110 cris_prepare_dyn_jmp(dc);
1926 2111 return 2;
1927 2112 }
... ... @@ -1933,7 +2118,7 @@ static unsigned int dec_jas_r(DisasContext *dc)
1933 2118 cris_cc_mask(dc, 0);
1934 2119 /* Stor the return address in Pd. */
1935 2120 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1936   - gen_op_movl_btarget_T0();
  2121 + t_gen_mov_env_TN(btarget, cpu_T[0]);
1937 2122 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
1938 2123 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1939 2124 cris_prepare_dyn_jmp(dc);
... ... @@ -1950,7 +2135,7 @@ static unsigned int dec_jas_im(DisasContext *dc)
1950 2135 cris_cc_mask(dc, 0);
1951 2136 /* Stor the return address in Pd. */
1952 2137 tcg_gen_movi_tl(cpu_T[0], imm);
1953   - gen_op_movl_btarget_T0();
  2138 + t_gen_mov_env_TN(btarget, cpu_T[0]);
1954 2139 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
1955 2140 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1956 2141 cris_prepare_dyn_jmp(dc);
... ... @@ -1967,7 +2152,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
1967 2152 cris_cc_mask(dc, 0);
1968 2153 /* Stor the return address in Pd. */
1969 2154 tcg_gen_movi_tl(cpu_T[0], imm);
1970   - gen_op_movl_btarget_T0();
  2155 + t_gen_mov_env_TN(btarget, cpu_T[0]);
1971 2156 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
1972 2157 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1973 2158 cris_prepare_dyn_jmp(dc);
... ... @@ -1980,7 +2165,7 @@ static unsigned int dec_jasc_r(DisasContext *dc)
1980 2165 cris_cc_mask(dc, 0);
1981 2166 /* Stor the return address in Pd. */
1982 2167 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1983   - gen_op_movl_btarget_T0();
  2168 + t_gen_mov_env_TN(btarget, cpu_T[0]);
1984 2169 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
1985 2170 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1986 2171 cris_prepare_dyn_jmp(dc);
... ... @@ -2016,7 +2201,7 @@ static unsigned int dec_bas_im(DisasContext *dc)
2016 2201 cris_cc_mask(dc, 0);
2017 2202 /* Stor the return address in Pd. */
2018 2203 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2019   - gen_op_movl_btarget_T0();
  2204 + t_gen_mov_env_TN(btarget, cpu_T[0]);
2020 2205 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2021 2206 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2022 2207 cris_prepare_dyn_jmp(dc);
... ... @@ -2032,7 +2217,7 @@ static unsigned int dec_basc_im(DisasContext *dc)
2032 2217 cris_cc_mask(dc, 0);
2033 2218 /* Stor the return address in Pd. */
2034 2219 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2035   - gen_op_movl_btarget_T0();
  2220 + t_gen_mov_env_TN(btarget, cpu_T[0]);
2036 2221 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2037 2222 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2038 2223 cris_prepare_dyn_jmp(dc);
... ... @@ -2062,7 +2247,7 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
2062 2247 case 6:
2063 2248 /* break. */
2064 2249 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2065   - gen_op_movl_pc_T0();
  2250 + t_gen_mov_env_TN(pc, cpu_T[0]);
2066 2251 /* Breaks start at 16 in the exception vector. */
2067 2252 gen_op_break_im(dc->op1 + 16);
2068 2253 dc->is_jmp = DISAS_SWI;
... ... @@ -2247,7 +2432,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
2247 2432 if (env->breakpoints[j] == dc->pc) {
2248 2433 cris_evaluate_flags (dc);
2249 2434 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2250   - gen_op_movl_pc_T0();
  2435 + t_gen_mov_env_TN(pc, cpu_T[0]);
2251 2436 gen_op_debug();
2252 2437 dc->is_jmp = DISAS_UPDATE;
2253 2438 }
... ... @@ -2279,6 +2464,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2279 2464 dc->singlestep_enabled = env->singlestep_enabled;
2280 2465 dc->flagx_live = 0;
2281 2466 dc->flags_x = 0;
  2467 +
2282 2468 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2283 2469 lj = -1;
2284 2470 do
... ... @@ -2333,8 +2519,8 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2333 2519 && dc->pc < next_page_start);
2334 2520  
2335 2521 if (!dc->is_jmp) {
2336   - gen_op_movl_T0_im((long)dc->pc);
2337   - gen_op_movl_pc_T0();
  2522 + tcg_gen_movi_tl(cpu_T[0], dc->pc);
  2523 + t_gen_mov_env_TN(pc, cpu_T[0]);
2338 2524 }
2339 2525  
2340 2526 cris_evaluate_flags (dc);
... ...