gwj / at91sam9263 · Commits

Commit 30b6f3a866ba4cec86b86ddd22cf3fba3f23ea1d

Authored by ths
1 parent 0f78cf0c

Initialize more GT64xxx registers on reset. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2956 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 113 additions and 11 deletions
hw/gt64xxx.c
  View file @30b6f3a
@@ -865,19 +865,31 @@ void gt64120_reset(void *opaque) @@ -865,19 +865,31 @@ void gt64120_reset(void *opaque)
865 { 865 {
866 GT64120State *s = opaque; 866 GT64120State *s = opaque;
867 867
  868 + /* FIXME: Malta specific hw assumptions ahead */
  869 +
868 /* CPU Configuration */ 870 /* CPU Configuration */
869 #ifdef TARGET_WORDS_BIGENDIAN 871 #ifdef TARGET_WORDS_BIGENDIAN
870 s->regs[GT_CPU] = 0x00000000; 872 s->regs[GT_CPU] = 0x00000000;
871 #else 873 #else
872 s->regs[GT_CPU] = 0x00001000; 874 s->regs[GT_CPU] = 0x00001000;
873 #endif 875 #endif
874 - s->regs[GT_MULTI] = 0x00000000; 876 + s->regs[GT_MULTI] = 0x00000003;
  877 +
  878 + /* CPU Address decode */
  879 + s->regs[GT_SCS10LD] = 0x00000000;
  880 + s->regs[GT_SCS10HD] = 0x00000007;
  881 + s->regs[GT_SCS32LD] = 0x00000008;
  882 + s->regs[GT_SCS32HD] = 0x0000000f;
  883 + s->regs[GT_CS20LD] = 0x000000e0;
  884 + s->regs[GT_CS20HD] = 0x00000070;
  885 + s->regs[GT_CS3BOOTLD] = 0x000000f8;
  886 + s->regs[GT_CS3BOOTHD] = 0x0000007f;
875 887
876 - /* CPU Address decode FIXME: not complete*/  
877 s->regs[GT_PCI0IOLD] = 0x00000080; 888 s->regs[GT_PCI0IOLD] = 0x00000080;
878 s->regs[GT_PCI0IOHD] = 0x0000000f; 889 s->regs[GT_PCI0IOHD] = 0x0000000f;
879 s->regs[GT_PCI0M0LD] = 0x00000090; 890 s->regs[GT_PCI0M0LD] = 0x00000090;
880 s->regs[GT_PCI0M0HD] = 0x0000001f; 891 s->regs[GT_PCI0M0HD] = 0x0000001f;
  892 + s->regs[GT_ISD] = 0x000000a0;
881 s->regs[GT_PCI0M1LD] = 0x00000790; 893 s->regs[GT_PCI0M1LD] = 0x00000790;
882 s->regs[GT_PCI0M1HD] = 0x0000001f; 894 s->regs[GT_PCI0M1HD] = 0x0000001f;
883 s->regs[GT_PCI1IOLD] = 0x00000100; 895 s->regs[GT_PCI1IOLD] = 0x00000100;
@@ -886,6 +898,12 @@ void gt64120_reset(void *opaque) @@ -886,6 +898,12 @@ void gt64120_reset(void *opaque)
886 s->regs[GT_PCI1M0HD] = 0x0000001f; 898 s->regs[GT_PCI1M0HD] = 0x0000001f;
887 s->regs[GT_PCI1M1LD] = 0x00000120; 899 s->regs[GT_PCI1M1LD] = 0x00000120;
888 s->regs[GT_PCI1M1HD] = 0x0000002f; 900 s->regs[GT_PCI1M1HD] = 0x0000002f;
  901 +
  902 + s->regs[GT_SCS10AR] = 0x00000000;
  903 + s->regs[GT_SCS32AR] = 0x00000008;
  904 + s->regs[GT_CS20R] = 0x000000e0;
  905 + s->regs[GT_CS3BOOTR] = 0x000000f8;
  906 +
889 s->regs[GT_PCI0IOREMAP] = 0x00000080; 907 s->regs[GT_PCI0IOREMAP] = 0x00000080;
890 s->regs[GT_PCI0M0REMAP] = 0x00000090; 908 s->regs[GT_PCI0M0REMAP] = 0x00000090;
891 s->regs[GT_PCI0M1REMAP] = 0x00000790; 909 s->regs[GT_PCI0M1REMAP] = 0x00000790;
@@ -900,6 +918,43 @@ void gt64120_reset(void *opaque) @@ -900,6 +918,43 @@ void gt64120_reset(void *opaque)
900 s->regs[GT_CPUERR_DATAHI] = 0xffffffff; 918 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
901 s->regs[GT_CPUERR_PARITY] = 0x000000ff; 919 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
902 920
  921 + /* CPU Sync Barrier */
  922 + s->regs[GT_PCI0SYNC] = 0x00000000;
  923 + s->regs[GT_PCI1SYNC] = 0x00000000;
  924 +
  925 + /* SDRAM and Device Address Decode */
  926 + s->regs[GT_SCS0LD] = 0x00000000;
  927 + s->regs[GT_SCS0HD] = 0x00000007;
  928 + s->regs[GT_SCS1LD] = 0x00000008;
  929 + s->regs[GT_SCS1HD] = 0x0000000f;
  930 + s->regs[GT_SCS2LD] = 0x00000010;
  931 + s->regs[GT_SCS2HD] = 0x00000017;
  932 + s->regs[GT_SCS3LD] = 0x00000018;
  933 + s->regs[GT_SCS3HD] = 0x0000001f;
  934 + s->regs[GT_CS0LD] = 0x000000c0;
  935 + s->regs[GT_CS0HD] = 0x000000c7;
  936 + s->regs[GT_CS1LD] = 0x000000c8;
  937 + s->regs[GT_CS1HD] = 0x000000cf;
  938 + s->regs[GT_CS2LD] = 0x000000d0;
  939 + s->regs[GT_CS2HD] = 0x000000df;
  940 + s->regs[GT_CS3LD] = 0x000000f0;
  941 + s->regs[GT_CS3HD] = 0x000000fb;
  942 + s->regs[GT_BOOTLD] = 0x000000fc;
  943 + s->regs[GT_BOOTHD] = 0x000000ff;
  944 + s->regs[GT_ADERR] = 0xffffffff;
  945 +
  946 + /* SDRAM Configuration */
  947 + s->regs[GT_SDRAM_CFG] = 0x00000200;
  948 + s->regs[GT_SDRAM_OPMODE] = 0x00000000;
  949 + s->regs[GT_SDRAM_BM] = 0x00000007;
  950 + s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
  951 +
  952 + /* SDRAM Parameters */
  953 + s->regs[GT_SDRAM_B0] = 0x00000005;
  954 + s->regs[GT_SDRAM_B1] = 0x00000005;
  955 + s->regs[GT_SDRAM_B2] = 0x00000005;
  956 + s->regs[GT_SDRAM_B3] = 0x00000005;
  957 +
903 /* ECC */ 958 /* ECC */
904 s->regs[GT_ECC_ERRDATALO] = 0x00000000; 959 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
905 s->regs[GT_ECC_ERRDATAHI] = 0x00000000; 960 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
@@ -907,22 +962,69 @@ void gt64120_reset(void *opaque) @@ -907,22 +962,69 @@ void gt64120_reset(void *opaque)
907 s->regs[GT_ECC_CALC] = 0x00000000; 962 s->regs[GT_ECC_CALC] = 0x00000000;
908 s->regs[GT_ECC_ERRADDR] = 0x00000000; 963 s->regs[GT_ECC_ERRADDR] = 0x00000000;
909 964
910 - /* SDRAM Parameters */  
911 - s->regs[GT_SDRAM_B0] = 0x00000005;  
912 - s->regs[GT_SDRAM_B1] = 0x00000005;  
913 - s->regs[GT_SDRAM_B2] = 0x00000005;  
914 - s->regs[GT_SDRAM_B3] = 0x00000005; 965 + /* Device Parameters */
  966 + s->regs[GT_DEV_B0] = 0x386fffff;
  967 + s->regs[GT_DEV_B1] = 0x386fffff;
  968 + s->regs[GT_DEV_B2] = 0x386fffff;
  969 + s->regs[GT_DEV_B3] = 0x386fffff;
  970 + s->regs[GT_DEV_BOOT] = 0x146fffff;
915 971
916 - /* PCI Internal FIXME: not complete*/ 972 + /* DMA registers are all zeroed at reset */
  973 +
  974 + /* Timer/Counter */
  975 + s->regs[GT_TC0] = 0xffffffff;
  976 + s->regs[GT_TC1] = 0x00ffffff;
  977 + s->regs[GT_TC2] = 0x00ffffff;
  978 + s->regs[GT_TC3] = 0x00ffffff;
  979 + s->regs[GT_TC_CONTROL] = 0x00000000;
  980 +
  981 + /* PCI Internal */
917 #ifdef TARGET_WORDS_BIGENDIAN 982 #ifdef TARGET_WORDS_BIGENDIAN
918 s->regs[GT_PCI0_CMD] = 0x00000000; 983 s->regs[GT_PCI0_CMD] = 0x00000000;
919 - s->regs[GT_PCI1_CMD] = 0x00000000;  
920 #else 984 #else
921 s->regs[GT_PCI0_CMD] = 0x00010001; 985 s->regs[GT_PCI0_CMD] = 0x00010001;
922 - s->regs[GT_PCI1_CMD] = 0x00010001;  
923 #endif 986 #endif
924 - s->regs[GT_PCI0_IACK] = 0x00000000; 987 + s->regs[GT_PCI0_TOR] = 0x0000070f;
  988 + s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
  989 + s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
  990 + s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
  991 + s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
925 s->regs[GT_PCI1_IACK] = 0x00000000; 992 s->regs[GT_PCI1_IACK] = 0x00000000;
  993 + s->regs[GT_PCI0_IACK] = 0x00000000;
  994 + s->regs[GT_PCI0_BARE] = 0x0000000f;
  995 + s->regs[GT_PCI0_PREFMBR] = 0x00000040;
  996 + s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
  997 + s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
  998 + s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
  999 + s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
  1000 + s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
  1001 + s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
  1002 + s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
  1003 +#ifdef TARGET_WORDS_BIGENDIAN
  1004 + s->regs[GT_PCI1_CMD] = 0x00000000;
  1005 +#else
  1006 + s->regs[GT_PCI1_CMD] = 0x00010001;
  1007 +#endif
  1008 + s->regs[GT_PCI1_TOR] = 0x0000070f;
  1009 + s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
  1010 + s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
  1011 + s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
  1012 + s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
  1013 + s->regs[GT_PCI1_BARE] = 0x0000000f;
  1014 + s->regs[GT_PCI1_PREFMBR] = 0x00000040;
  1015 + s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
  1016 + s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
  1017 + s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
  1018 + s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
  1019 + s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
  1020 + s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
  1021 + s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
  1022 + s->regs[GT_PCI1_CFGADDR] = 0x00000000;
  1023 + s->regs[GT_PCI1_CFGDATA] = 0x00000000;
  1024 + s->regs[GT_PCI0_CFGADDR] = 0x00000000;
  1025 + s->regs[GT_PCI0_CFGDATA] = 0x00000000;
  1026 +
  1027 + /* Interrupt registers are all zeroed at reset */
926 1028
927 gt64120_pci_mapping(s); 1029 gt64120_pci_mapping(s);
928 } 1030 }