gwj / at91sam9263 · Commits

Commit 30abcfc7babe4bde680e1a04a1a6d0f1c041cc29

Authored by edgar_igl
1 parent 9bcd77d6

CRIS: Restructure the translator to allow for better code generation. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4594 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 544 additions and 386 deletions
target-cris/cpu.h
  View file @30abcfc
... ... @@ -120,8 +120,7 @@ typedef struct CPUCRISState {
120 120 uint32_t cc_result;
121 121 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
122 122 int cc_size;
123   - /* Extended arithmetics. */
124   - int cc_x_live;
  123 + /* X flag at the time of cc snapshot. */
125 124 int cc_x;
126 125  
127 126 int exception_index;
... ... @@ -130,10 +129,6 @@ typedef struct CPUCRISState {
130 129 int fault_vector;
131 130 int trap_vector;
132 131  
133   - uint32_t debug1;
134   - uint32_t debug2;
135   - uint32_t debug3;
136   -
137 132 /* FIXME: add a check in the translator to avoid writing to support
138 133 register sets beyond the 4th. The ISA allows up to 256! but in
139 134 practice there is no core that implements more than 4.
... ... @@ -177,20 +172,14 @@ void do_interrupt(CPUCRISState *env);
177 172 is returned if the signal was handled by the virtual CPU. */
178 173 int cpu_cris_signal_handler(int host_signum, void *pinfo,
179 174 void *puc);
180   -void cpu_cris_flush_flags(CPUCRISState *, int);
181   -
182   -
183 175 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
184 176 int is_asi);
185 177  
186 178 enum {
187 179 CC_OP_DYNAMIC, /* Use env->cc_op */
188 180 CC_OP_FLAGS,
189   - CC_OP_LOGIC,
190 181 CC_OP_CMP,
191 182 CC_OP_MOVE,
192   - CC_OP_MOVE_PD,
193   - CC_OP_MOVE_SD,
194 183 CC_OP_ADD,
195 184 CC_OP_ADDC,
196 185 CC_OP_MCP,
... ... @@ -213,32 +202,6 @@ enum {
213 202 CC_OP_LZ
214 203 };
215 204  
216   -#define CCF_C 0x01
217   -#define CCF_V 0x02
218   -#define CCF_Z 0x04
219   -#define CCF_N 0x08
220   -#define CCF_X 0x10
221   -
222   -#define CRIS_SSP 0
223   -#define CRIS_USP 1
224   -
225   -void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector);
226   -void cris_set_macsr(CPUCRISState *env, uint32_t val);
227   -void cris_switch_sp(CPUCRISState *env);
228   -
229   -void do_cris_semihosting(CPUCRISState *env, int nr);
230   -
231   -enum cris_features {
232   - CRIS_FEATURE_CF_ISA_MUL,
233   -};
234   -
235   -static inline int cris_feature(CPUCRISState *env, int feature)
236   -{
237   - return (env->features & (1u << feature)) != 0;
238   -}
239   -
240   -void register_cris_insns (CPUCRISState *env);
241   -
242 205 /* CRIS uses 8k pages. */
243 206 #define TARGET_PAGE_BITS 13
244 207 #define MMAP_SHIFT TARGET_PAGE_BITS
... ...
target-cris/helper.c
  View file @30abcfc
... ... @@ -42,9 +42,8 @@ int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
42 42 int mmu_idx, int is_softmmu)
43 43 {
44 44 env->exception_index = 0xaa;
45   - env->debug1 = address;
  45 + env->pregs[PR_EDA] = address;
46 46 cpu_dump_state(env, stderr, fprintf, 0);
47   - env->pregs[PR_ERP] = env->pc;
48 47 return 1;
49 48 }
50 49  
... ...
target-cris/helper.h
  View file @30abcfc
... ... @@ -2,7 +2,6 @@
2 2  
3 3 void TCG_HELPER_PROTO helper_raise_exception(uint32_t index);
4 4 void TCG_HELPER_PROTO helper_tlb_flush_pid(uint32_t pid);
5   -void TCG_HELPER_PROTO helper_tlb_flush(void);
6 5 void TCG_HELPER_PROTO helper_dump(uint32_t a0, uint32_t a1, uint32_t a2);
7 6 void TCG_HELPER_PROTO helper_dummy(void);
8 7 void TCG_HELPER_PROTO helper_rfe(void);
... ... @@ -18,3 +17,4 @@ void TCG_HELPER_PROTO helper_evaluate_flags_alu_4(void);
18 17 void TCG_HELPER_PROTO helper_evaluate_flags_move_4 (void);
19 18 void TCG_HELPER_PROTO helper_evaluate_flags_move_2 (void);
20 19 void TCG_HELPER_PROTO helper_evaluate_flags (void);
  20 +void TCG_HELPER_PROTO helper_top_evaluate_flags(void);
... ...
target-cris/op_helper.c
  View file @30abcfc
... ... @@ -22,6 +22,7 @@
22 22 #include <assert.h>
23 23 #include "exec.h"
24 24 #include "mmu.h"
  25 +#include "helper.h"
25 26  
26 27 #define MMUSUFFIX _mmu
27 28  
... ... @@ -67,6 +68,9 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
67 68 /* the PC is inside the translated code. It means that we have
68 69 a virtual CPU fault */
69 70 cpu_restore_state(tb, env, pc, NULL);
  71 +
  72 + /* Evaluate flags after retranslation. */
  73 + helper_top_evaluate_flags();
70 74 }
71 75 }
72 76 cpu_loop_exit();
... ... @@ -87,12 +91,7 @@ void helper_tlb_flush_pid(uint32_t pid)
87 91 #endif
88 92 }
89 93  
90   -void helper_tlb_flush(void)
91   -{
92   - tlb_flush(env, 1);
93   -}
94   -
95   -void helper_dump(uint32_t a0, uint32_t a1)
  94 +void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
96 95 {
97 96 (fprintf(logfile, "%s: a0=%x a1=%x\n", __func__, a0, a1));
98 97 }
... ... @@ -236,13 +235,7 @@ static void evaluate_flags_writeback(uint32_t flags)
236 235 int x;
237 236  
238 237 /* Extended arithmetics, leave the z flag alone. */
239   - env->debug3 = env->pregs[PR_CCS];
240   -
241   - if (env->cc_x_live)
242   - x = env->cc_x;
243   - else
244   - x = env->pregs[PR_CCS] & X_FLAG;
245   -
  238 + x = env->cc_x;
246 239 if ((x || env->cc_op == CC_OP_ADDC)
247 240 && flags & Z_FLAG)
248 241 env->cc_mask &= ~Z_FLAG;
... ... @@ -359,7 +352,23 @@ void helper_evaluate_flags_alu_4(void)
359 352  
360 353 src = env->cc_src;
361 354 dst = env->cc_dest;
362   - res = env->cc_result;
  355 +
  356 + /* Reconstruct the result. */
  357 + switch (env->cc_op)
  358 + {
  359 + case CC_OP_SUB:
  360 + res = dst - src;
  361 + break;
  362 + case CC_OP_ADD:
  363 + res = dst + src;
  364 + break;
  365 + default:
  366 + res = env->cc_result;
  367 + break;
  368 + }
  369 +
  370 + if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
  371 + src = ~src;
363 372  
364 373 if ((res & 0x80000000L) != 0L)
365 374 {
... ... @@ -396,11 +405,9 @@ void helper_evaluate_flags_alu_4(void)
396 405  
397 406 void helper_evaluate_flags_move_4 (void)
398 407 {
399   - uint32_t src;
400 408 uint32_t res;
401 409 uint32_t flags = 0;
402 410  
403   - src = env->cc_src;
404 411 res = env->cc_result;
405 412  
406 413 if ((int32_t)res < 0)
... ... @@ -440,6 +447,8 @@ void helper_evaluate_flags (void)
440 447 dst = env->cc_dest;
441 448 res = env->cc_result;
442 449  
  450 + if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
  451 + src = ~src;
443 452  
444 453 /* Now, evaluate the flags. This stuff is based on
445 454 Per Zander's CRISv10 simulator. */
... ... @@ -548,3 +557,55 @@ void helper_evaluate_flags (void)
548 557 }
549 558 evaluate_flags_writeback(flags);
550 559 }
  560 +
  561 +void helper_top_evaluate_flags(void)
  562 +{
  563 + switch (env->cc_op)
  564 + {
  565 + case CC_OP_MCP:
  566 + helper_evaluate_flags_mcp();
  567 + break;
  568 + case CC_OP_MULS:
  569 + helper_evaluate_flags_muls();
  570 + break;
  571 + case CC_OP_MULU:
  572 + helper_evaluate_flags_mulu();
  573 + break;
  574 + case CC_OP_MOVE:
  575 + case CC_OP_AND:
  576 + case CC_OP_OR:
  577 + case CC_OP_XOR:
  578 + case CC_OP_ASR:
  579 + case CC_OP_LSR:
  580 + case CC_OP_LSL:
  581 + switch (env->cc_size)
  582 + {
  583 + case 4:
  584 + helper_evaluate_flags_move_4();
  585 + break;
  586 + case 2:
  587 + helper_evaluate_flags_move_2();
  588 + break;
  589 + default:
  590 + helper_evaluate_flags();
  591 + break;
  592 + }
  593 + break;
  594 + case CC_OP_FLAGS:
  595 + /* live. */
  596 + break;
  597 + default:
  598 + {
  599 + switch (env->cc_size)
  600 + {
  601 + case 4:
  602 + helper_evaluate_flags_alu_4();
  603 + break;
  604 + default:
  605 + helper_evaluate_flags();
  606 + break;
  607 + }
  608 + }
  609 + break;
  610 + }
  611 +}
... ...
target-cris/translate.c
  View file @30abcfc
... ... @@ -65,6 +65,7 @@ TCGv cpu_env;
65 65 TCGv cpu_T[2];
66 66 TCGv cpu_R[16];
67 67 TCGv cpu_PR[16];
  68 +TCGv cc_x;
68 69 TCGv cc_src;
69 70 TCGv cc_dest;
70 71 TCGv cc_result;
... ... @@ -93,12 +94,16 @@ typedef struct DisasContext {
93 94 int cc_op;
94 95 int cc_size;
95 96 uint32_t cc_mask;
96   - int flags_live; /* Wether or not $ccs is uptodate. */
97   - int flagx_live; /* Wether or not flags_x has the x flag known at
98   - translation time. */
  97 +
  98 + int cc_size_uptodate; /* -1 invalid or last written value. */
  99 +
  100 + int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
  101 + int flags_uptodate; /* Wether or not $ccs is uptodate. */
  102 + int flagx_known; /* Wether or not flags_x has the x flag known at
  103 + translation time. */
99 104 int flags_x;
100   - int clear_x; /* Clear x after this insn? */
101 105  
  106 + int clear_x; /* Clear x after this insn? */
102 107 int user; /* user or kernel mode. */
103 108 int is_jmp;
104 109  
... ... @@ -267,8 +272,8 @@ static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
267 272 tcg_gen_shri_i64(t0, t0, 32);
268 273 tcg_gen_trunc_i64_i32(d2, t0);
269 274  
270   - tcg_gen_discard_i64(t0);
271   - tcg_gen_discard_i64(t1);
  275 + tcg_temp_free(t0);
  276 + tcg_temp_free(t1);
272 277 }
273 278  
274 279 /* 64-bit unsigned muls, lower result in d and upper in d2. */
... ... @@ -287,8 +292,8 @@ static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
287 292 tcg_gen_shri_i64(t0, t0, 32);
288 293 tcg_gen_trunc_i64_i32(d2, t0);
289 294  
290   - tcg_gen_discard_i64(t0);
291   - tcg_gen_discard_i64(t1);
  295 + tcg_temp_free(t0);
  296 + tcg_temp_free(t1);
292 297 }
293 298  
294 299 /* 32bit branch-free binary search for counting leading zeros. */
... ... @@ -354,15 +359,16 @@ static void t_gen_lz_i32(TCGv d, TCGv x)
354 359 tcg_gen_addi_i32(d, n, 2);
355 360 tcg_gen_sub_i32(d, d, m);
356 361  
357   - tcg_gen_discard_i32(y);
358   - tcg_gen_discard_i32(m);
359   - tcg_gen_discard_i32(n);
  362 + tcg_temp_free(y);
  363 + tcg_temp_free(m);
  364 + tcg_temp_free(n);
360 365 }
361 366  
362   -static void t_gen_btst(TCGv d, TCGv s)
  367 +static void t_gen_btst(TCGv d, TCGv a, TCGv b)
363 368 {
364 369 TCGv sbit;
365 370 TCGv bset;
  371 + TCGv t0;
366 372 int l1;
367 373  
368 374 /* des ref:
... ... @@ -390,18 +396,19 @@ static void t_gen_btst(TCGv d, TCGv s)
390 396 l1 = gen_new_label();
391 397 sbit = tcg_temp_new(TCG_TYPE_TL);
392 398 bset = tcg_temp_new(TCG_TYPE_TL);
  399 + t0 = tcg_temp_new(TCG_TYPE_TL);
393 400  
394 401 /* Compute bset and sbit. */
395   - tcg_gen_andi_tl(sbit, s, 31);
396   - tcg_gen_shl_tl(s, tcg_const_tl(1), sbit);
397   - tcg_gen_and_tl(bset, d, s);
  402 + tcg_gen_andi_tl(sbit, b, 31);
  403 + tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
  404 + tcg_gen_and_tl(bset, a, t0);
398 405 tcg_gen_shr_tl(bset, bset, sbit);
399 406 /* Displace to N_FLAG. */
400 407 tcg_gen_shli_tl(bset, bset, 3);
401 408  
402 409 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
403 410 tcg_gen_subi_tl(sbit, sbit, 1);
404   - tcg_gen_and_tl(sbit, d, sbit);
  411 + tcg_gen_and_tl(sbit, a, sbit);
405 412  
406 413 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
407 414 /* or in the N_FLAG. */
... ... @@ -411,11 +418,11 @@ static void t_gen_btst(TCGv d, TCGv s)
411 418 tcg_gen_ori_tl(d, d, Z_FLAG);
412 419 gen_set_label(l1);
413 420  
414   - tcg_gen_discard_tl(sbit);
415   - tcg_gen_discard_tl(bset);
  421 + tcg_temp_free(sbit);
  422 + tcg_temp_free(bset);
416 423 }
417 424  
418   -static void t_gen_cris_dstep(TCGv d, TCGv s)
  425 +static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
419 426 {
420 427 int l1;
421 428  
... ... @@ -426,9 +433,9 @@ static void t_gen_cris_dstep(TCGv d, TCGv s)
426 433 * if (d >= s)
427 434 * d -= s;
428 435 */
429   - tcg_gen_shli_tl(d, d, 1);
430   - tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1);
431   - tcg_gen_sub_tl(d, d, s);
  436 + tcg_gen_shli_tl(d, a, 1);
  437 + tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
  438 + tcg_gen_sub_tl(d, d, b);
432 439 gen_set_label(l1);
433 440 }
434 441  
... ... @@ -444,32 +451,56 @@ static inline void t_gen_add_flag(TCGv d, int flag)
444 451 if (flag)
445 452 tcg_gen_shri_tl(c, c, flag);
446 453 tcg_gen_add_tl(d, d, c);
447   - tcg_gen_discard_tl(c);
  454 + tcg_temp_free(c);
448 455 }
449 456  
450   -static inline void t_gen_addx_carry(TCGv d)
  457 +static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
451 458 {
452   - TCGv x, c;
  459 + if (dc->flagx_known) {
  460 + if (dc->flags_x) {
  461 + TCGv c;
  462 +
  463 + c = tcg_temp_new(TCG_TYPE_TL);
  464 + t_gen_mov_TN_preg(c, PR_CCS);
  465 + /* C flag is already at bit 0. */
  466 + tcg_gen_andi_tl(c, c, C_FLAG);
  467 + tcg_gen_add_tl(d, d, c);
  468 + tcg_temp_free(c);
  469 + }
  470 + } else {
  471 + TCGv x, c;
453 472  
454   - x = tcg_temp_new(TCG_TYPE_TL);
455   - c = tcg_temp_new(TCG_TYPE_TL);
456   - t_gen_mov_TN_preg(x, PR_CCS);
457   - tcg_gen_mov_tl(c, x);
  473 + x = tcg_temp_new(TCG_TYPE_TL);
  474 + c = tcg_temp_new(TCG_TYPE_TL);
  475 + t_gen_mov_TN_preg(x, PR_CCS);
  476 + tcg_gen_mov_tl(c, x);
458 477  
459   - /* Propagate carry into d if X is set. Branch free. */
460   - tcg_gen_andi_tl(c, c, C_FLAG);
461   - tcg_gen_andi_tl(x, x, X_FLAG);
462   - tcg_gen_shri_tl(x, x, 4);
  478 + /* Propagate carry into d if X is set. Branch free. */
  479 + tcg_gen_andi_tl(c, c, C_FLAG);
  480 + tcg_gen_andi_tl(x, x, X_FLAG);
  481 + tcg_gen_shri_tl(x, x, 4);
463 482  
464   - tcg_gen_and_tl(x, x, c);
465   - tcg_gen_add_tl(d, d, x);
466   - tcg_gen_discard_tl(x);
467   - tcg_gen_discard_tl(c);
  483 + tcg_gen_and_tl(x, x, c);
  484 + tcg_gen_add_tl(d, d, x);
  485 + tcg_temp_free(x);
  486 + tcg_temp_free(c);
  487 + }
468 488 }
469 489  
470 490 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
471 491 {
472   - if (dc->flagx_live) {
  492 + if (dc->flagx_known) {
  493 + if (dc->flags_x) {
  494 + TCGv c;
  495 +
  496 + c = tcg_temp_new(TCG_TYPE_TL);
  497 + t_gen_mov_TN_preg(c, PR_CCS);
  498 + /* C flag is already at bit 0. */
  499 + tcg_gen_andi_tl(c, c, C_FLAG);
  500 + tcg_gen_sub_tl(d, d, c);
  501 + tcg_temp_free(c);
  502 + }
  503 + } else {
473 504 TCGv x, c;
474 505  
475 506 x = tcg_temp_new(TCG_TYPE_TL);
... ... @@ -484,18 +515,8 @@ static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
484 515  
485 516 tcg_gen_and_tl(x, x, c);
486 517 tcg_gen_sub_tl(d, d, x);
487   - tcg_gen_discard_tl(x);
488   - tcg_gen_discard_tl(c);
489   - } else {
490   - if (dc->flags_x) {
491   - TCGv c;
492   -
493   - c = tcg_temp_new(TCG_TYPE_TL);
494   - /* C flag is already at bit 0. */
495   - tcg_gen_andi_tl(c, c, C_FLAG);
496   - tcg_gen_add_tl(d, d, c);
497   - tcg_gen_discard_tl(c);
498   - }
  518 + tcg_temp_free(x);
  519 + tcg_temp_free(c);
499 520 }
500 521 }
501 522  
... ... @@ -515,8 +536,8 @@ static inline void t_gen_swapb(TCGv d, TCGv s)
515 536 tcg_gen_shri_tl(t, org_s, 8);
516 537 tcg_gen_andi_tl(t, t, 0x00ff00ff);
517 538 tcg_gen_or_tl(d, d, t);
518   - tcg_gen_discard_tl(t);
519   - tcg_gen_discard_tl(org_s);
  539 + tcg_temp_free(t);
  540 + tcg_temp_free(org_s);
520 541 }
521 542  
522 543 /* Swap the halfwords of the s operand. */
... ... @@ -529,7 +550,7 @@ static inline void t_gen_swapw(TCGv d, TCGv s)
529 550 tcg_gen_shli_tl(d, t, 16);
530 551 tcg_gen_shri_tl(t, t, 16);
531 552 tcg_gen_or_tl(d, d, t);
532   - tcg_gen_discard_tl(t);
  553 + tcg_temp_free(t);
533 554 }
534 555  
535 556 /* Reverse the within each byte.
... ... @@ -576,8 +597,8 @@ static inline void t_gen_swapr(TCGv d, TCGv s)
576 597 tcg_gen_andi_tl(t, t, bitrev[i].mask);
577 598 tcg_gen_or_tl(d, d, t);
578 599 }
579   - tcg_gen_discard_tl(t);
580   - tcg_gen_discard_tl(org_s);
  600 + tcg_temp_free(t);
  601 + tcg_temp_free(org_s);
581 602 }
582 603  
583 604 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
... ... @@ -595,7 +616,7 @@ static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
595 616 tcg_gen_mov_tl(env_pc, pc_true);
596 617 gen_set_label(l1);
597 618  
598   - tcg_gen_discard_tl(btaken);
  619 + tcg_temp_free(btaken);
599 620 }
600 621  
601 622 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
... ... @@ -627,20 +648,24 @@ static int sign_extend(unsigned int val, unsigned int width)
627 648  
628 649 static inline void cris_clear_x_flag(DisasContext *dc)
629 650 {
630   - if (!dc->flagx_live
631   - || (dc->flagx_live && dc->flags_x)
632   - || dc->cc_op == CC_OP_FLAGS)
633   - tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
634   - dc->flagx_live = 1;
  651 + dc->flagx_known = 1;
635 652 dc->flags_x = 0;
636 653 }
637 654  
638   -static void cris_evaluate_flags(DisasContext *dc)
  655 +static void cris_flush_cc_state(DisasContext *dc)
639 656 {
640   - if (!dc->flags_live) {
641   - tcg_gen_movi_tl(cc_op, dc->cc_op);
  657 + if (dc->cc_size_uptodate != dc->cc_size) {
642 658 tcg_gen_movi_tl(cc_size, dc->cc_size);
643   - tcg_gen_movi_tl(cc_mask, dc->cc_mask);
  659 + dc->cc_size_uptodate = dc->cc_size;
  660 + }
  661 + tcg_gen_movi_tl(cc_op, dc->cc_op);
  662 + tcg_gen_movi_tl(cc_mask, dc->cc_mask);
  663 +}
  664 +
  665 +static void cris_evaluate_flags(DisasContext *dc)
  666 +{
  667 + if (!dc->flags_uptodate) {
  668 + cris_flush_cc_state(dc);
644 669  
645 670 switch (dc->cc_op)
646 671 {
... ... @@ -654,6 +679,12 @@ static void cris_evaluate_flags(DisasContext *dc)
654 679 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
655 680 break;
656 681 case CC_OP_MOVE:
  682 + case CC_OP_AND:
  683 + case CC_OP_OR:
  684 + case CC_OP_XOR:
  685 + case CC_OP_ASR:
  686 + case CC_OP_LSR:
  687 + case CC_OP_LSL:
657 688 switch (dc->cc_size)
658 689 {
659 690 case 4:
... ... @@ -684,7 +715,7 @@ static void cris_evaluate_flags(DisasContext *dc)
684 715 }
685 716 break;
686 717 }
687   - dc->flags_live = 1;
  718 + dc->flags_uptodate = 1;
688 719 }
689 720 }
690 721  
... ... @@ -705,132 +736,144 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
705 736 if (mask == 0)
706 737 dc->update_cc = 0;
707 738 else
708   - dc->flags_live = 0;
  739 + dc->flags_uptodate = 0;
709 740 }
710 741  
711 742 static void cris_update_cc_op(DisasContext *dc, int op, int size)
712 743 {
713 744 dc->cc_op = op;
714 745 dc->cc_size = size;
715   - dc->flags_live = 0;
  746 + dc->flags_uptodate = 0;
716 747 }
717 748  
718   -/* op is the operation.
719   - T0, T1 are the operands.
720   - dst is the destination reg.
721   -*/
722   -static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
  749 +static inline void cris_update_cc_x(DisasContext *dc)
  750 +{
  751 + /* Save the x flag state at the time of the cc snapshot. */
  752 + if (dc->flagx_known) {
  753 + if (dc->cc_x_uptodate == (2 | dc->flags_x))
  754 + return;
  755 + tcg_gen_movi_tl(cc_x, dc->flags_x);
  756 + dc->cc_x_uptodate = 2 | dc->flags_x;
  757 + }
  758 + else {
  759 + tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
  760 + dc->cc_x_uptodate = 1;
  761 + }
  762 +}
  763 +
  764 +/* Update cc prior to executing ALU op. Needs source operands untouched. */
  765 +static void cris_pre_alu_update_cc(DisasContext *dc, int op,
  766 + TCGv dst, TCGv src, int size)
723 767 {
724   - int writeback = 1;
725 768 if (dc->update_cc) {
726 769 cris_update_cc_op(dc, op, size);
727   - if (op != CC_OP_MOVE)
728   - tcg_gen_mov_tl(cc_dest, cpu_T[0]);
  770 + tcg_gen_mov_tl(cc_src, src);
  771 +
  772 + if (op != CC_OP_MOVE
  773 + && op != CC_OP_AND
  774 + && op != CC_OP_OR
  775 + && op != CC_OP_XOR
  776 + && op != CC_OP_ASR
  777 + && op != CC_OP_LSR
  778 + && op != CC_OP_LSL)
  779 + tcg_gen_mov_tl(cc_dest, dst);
  780 +
  781 + cris_update_cc_x(dc);
  782 + }
  783 +}
729 784  
730   - /* FIXME: This shouldn't be needed. But we don't pass the
731   - tests without it. Investigate. */
732   - t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
733   - t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
  785 +/* Update cc after executing ALU op. needs the result. */
  786 +static inline void cris_update_result(DisasContext *dc, TCGv res)
  787 +{
  788 + if (dc->update_cc) {
  789 + if (dc->cc_size == 4 &&
  790 + (dc->cc_op == CC_OP_SUB
  791 + || dc->cc_op == CC_OP_ADD))
  792 + return;
  793 + tcg_gen_mov_tl(cc_result, res);
734 794 }
  795 +}
735 796  
  797 +/* Returns one if the write back stage should execute. */
  798 +static void cris_alu_op_exec(DisasContext *dc, int op,
  799 + TCGv dst, TCGv a, TCGv b, int size)
  800 +{
736 801 /* Emit the ALU insns. */
737 802 switch (op)
738 803 {
739 804 case CC_OP_ADD:
740   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  805 + tcg_gen_add_tl(dst, a, b);
741 806 /* Extended arithmetics. */
742   - t_gen_addx_carry(cpu_T[0]);
  807 + t_gen_addx_carry(dc, dst);
743 808 break;
744 809 case CC_OP_ADDC:
745   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
746   - t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
  810 + tcg_gen_add_tl(dst, a, b);
  811 + t_gen_add_flag(dst, 0); /* C_FLAG. */
747 812 break;
748 813 case CC_OP_MCP:
749   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
750   - t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
  814 + tcg_gen_add_tl(dst, a, b);
  815 + t_gen_add_flag(dst, 8); /* R_FLAG. */
751 816 break;
752 817 case CC_OP_SUB:
753   - tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
754   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
755   - tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
756   - /* CRIS flag evaluation needs ~src. */
757   - tcg_gen_not_tl(cpu_T[1], cpu_T[1]);
758   -
  818 + tcg_gen_sub_tl(dst, a, b);
759 819 /* Extended arithmetics. */
760   - t_gen_subx_carry(dc, cpu_T[0]);
  820 + t_gen_subx_carry(dc, dst);
761 821 break;
762 822 case CC_OP_MOVE:
763   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  823 + tcg_gen_mov_tl(dst, b);
764 824 break;
765 825 case CC_OP_OR:
766   - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  826 + tcg_gen_or_tl(dst, a, b);
767 827 break;
768 828 case CC_OP_AND:
769   - tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  829 + tcg_gen_and_tl(dst, a, b);
770 830 break;
771 831 case CC_OP_XOR:
772   - tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  832 + tcg_gen_xor_tl(dst, a, b);
773 833 break;
774 834 case CC_OP_LSL:
775   - t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
  835 + t_gen_lsl(dst, a, b);
776 836 break;
777 837 case CC_OP_LSR:
778   - t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
  838 + t_gen_lsr(dst, a, b);
779 839 break;
780 840 case CC_OP_ASR:
781   - t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
  841 + t_gen_asr(dst, a, b);
782 842 break;
783 843 case CC_OP_NEG:
784   - tcg_gen_neg_tl(cpu_T[0], cpu_T[1]);
  844 + tcg_gen_neg_tl(dst, b);
785 845 /* Extended arithmetics. */
786   - t_gen_subx_carry(dc, cpu_T[0]);
  846 + t_gen_subx_carry(dc, dst);
787 847 break;
788 848 case CC_OP_LZ:
789   - t_gen_lz_i32(cpu_T[0], cpu_T[1]);
  849 + t_gen_lz_i32(dst, b);
790 850 break;
791 851 case CC_OP_BTST:
792   - t_gen_btst(cpu_T[0], cpu_T[1]);
793   - writeback = 0;
  852 + t_gen_btst(dst, a, b);
794 853 break;
795 854 case CC_OP_MULS:
796   - {
797   - TCGv mof;
798   - mof = tcg_temp_new(TCG_TYPE_TL);
799   - t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
800   - t_gen_mov_preg_TN(dc, PR_MOF, mof);
801   - tcg_gen_discard_tl(mof);
802   - }
803   - break;
  855 + t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
  856 + break;
804 857 case CC_OP_MULU:
805   - {
806   - TCGv mof;
807   - mof = tcg_temp_new(TCG_TYPE_TL);
808   - t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
809   - t_gen_mov_preg_TN(dc, PR_MOF, mof);
810   - tcg_gen_discard_tl(mof);
811   - }
812   - break;
  858 + t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
  859 + break;
813 860 case CC_OP_DSTEP:
814   - t_gen_cris_dstep(cpu_T[0], cpu_T[1]);
  861 + t_gen_cris_dstep(dst, a, b);
815 862 break;
816 863 case CC_OP_BOUND:
817 864 {
818 865 int l1;
819 866 l1 = gen_new_label();
820   - tcg_gen_brcond_tl(TCG_COND_LEU,
821   - cpu_T[0], cpu_T[1], l1);
822   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
  867 + tcg_gen_mov_tl(dst, a);
  868 + tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
  869 + tcg_gen_mov_tl(dst, b);
823 870 gen_set_label(l1);
824 871 }
825 872 break;
826 873 case CC_OP_CMP:
827   - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
828   - /* CRIS flag evaluation needs ~src. */
829   - tcg_gen_not_tl(cpu_T[1], cpu_T[1]);
830   -
  874 + tcg_gen_sub_tl(dst, a, b);
831 875 /* Extended arithmetics. */
832   - t_gen_subx_carry(dc, cpu_T[0]);
833   - writeback = 0;
  876 + t_gen_subx_carry(dc, dst);
834 877 break;
835 878 default:
836 879 fprintf (logfile, "illegal ALU op.\n");
... ... @@ -838,40 +881,58 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
838 881 break;
839 882 }
840 883  
841   - if (dc->update_cc)
842   - tcg_gen_mov_tl(cc_src, cpu_T[1]);
843   -
844 884 if (size == 1)
845   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
  885 + tcg_gen_andi_tl(dst, dst, 0xff);
846 886 else if (size == 2)
847   - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
  887 + tcg_gen_andi_tl(dst, dst, 0xffff);
  888 +}
  889 +
  890 +static void cris_alu(DisasContext *dc, int op,
  891 + TCGv d, TCGv op_a, TCGv op_b, int size)
  892 +{
  893 + TCGv tmp;
  894 + int writeback;
  895 +
  896 + writeback = 1;
  897 + tmp = cpu_T[0];
  898 + if (op == CC_OP_CMP)
  899 + writeback = 0;
  900 + else if (size == 4) {
  901 + tmp = d;
  902 + writeback = 0;
  903 + }
  904 +
  905 + cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
  906 + cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
  907 + cris_update_result(dc, tmp);
848 908  
849 909 /* Writeback. */
850 910 if (writeback) {
851   - if (size == 4)
852   - tcg_gen_mov_tl(cpu_R[rd], cpu_T[0]);
853   - else {
854   - if (size == 1)
855   - tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xff);
856   - else
857   - tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xffff);
858   - tcg_gen_or_tl(cpu_R[rd], cpu_R[rd], cpu_T[0]);
859   - }
  911 + if (size == 1)
  912 + tcg_gen_andi_tl(d, d, ~0xff);
  913 + else
  914 + tcg_gen_andi_tl(d, d, ~0xffff);
  915 + tcg_gen_or_tl(d, d, tmp);
860 916 }
861   - if (dc->update_cc)
862   - tcg_gen_mov_tl(cc_result, cpu_T[0]);
863 917 }
864 918  
865 919 static int arith_cc(DisasContext *dc)
866 920 {
867 921 if (dc->update_cc) {
868 922 switch (dc->cc_op) {
  923 + case CC_OP_ADDC: return 1;
869 924 case CC_OP_ADD: return 1;
870 925 case CC_OP_SUB: return 1;
  926 + case CC_OP_DSTEP: return 1;
871 927 case CC_OP_LSL: return 1;
872 928 case CC_OP_LSR: return 1;
873 929 case CC_OP_ASR: return 1;
874 930 case CC_OP_CMP: return 1;
  931 + case CC_OP_NEG: return 1;
  932 + case CC_OP_OR: return 1;
  933 + case CC_OP_XOR: return 1;
  934 + case CC_OP_MULU: return 1;
  935 + case CC_OP_MULS: return 1;
875 936 default:
876 937 return 0;
877 938 }
... ... @@ -893,7 +954,7 @@ static void gen_tst_cc (DisasContext *dc, int cond)
893 954 * When this function is done, T0 should be non-zero if the condition
894 955 * code is true.
895 956 */
896   - arith_opt = arith_cc(dc) && !dc->flags_live;
  957 + arith_opt = arith_cc(dc) && !dc->flags_uptodate;
897 958 switch (cond) {
898 959 case CC_EQ:
899 960 if (arith_opt) {
... ... @@ -982,7 +1043,7 @@ static void gen_tst_cc (DisasContext *dc, int cond)
982 1043 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
983 1044 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
984 1045  
985   - tcg_gen_discard_tl(tmp);
  1046 + tcg_temp_free(tmp);
986 1047 }
987 1048 break;
988 1049 case CC_GE:
... ... @@ -1022,8 +1083,8 @@ static void gen_tst_cc (DisasContext *dc, int cond)
1022 1083 tcg_gen_and_tl(cpu_T[0], z, n);
1023 1084 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1024 1085  
1025   - tcg_gen_discard_tl(n);
1026   - tcg_gen_discard_tl(z);
  1086 + tcg_temp_free(n);
  1087 + tcg_temp_free(z);
1027 1088 }
1028 1089 break;
1029 1090 case CC_LE:
... ... @@ -1043,8 +1104,8 @@ static void gen_tst_cc (DisasContext *dc, int cond)
1043 1104 tcg_gen_or_tl(cpu_T[0], z, n);
1044 1105 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1045 1106  
1046   - tcg_gen_discard_tl(n);
1047   - tcg_gen_discard_tl(z);
  1107 + tcg_temp_free(n);
  1108 + tcg_temp_free(z);
1048 1109 }
1049 1110 break;
1050 1111 case CC_P:
... ... @@ -1089,7 +1150,6 @@ void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1089 1150 {
1090 1151 int mem_index = cpu_mmu_index(dc->env);
1091 1152  
1092   - cris_evaluate_flags(dc);
1093 1153 if (size == 1) {
1094 1154 if (sign)
1095 1155 tcg_gen_qemu_ld8s(dst, addr, mem_index);
... ... @@ -1103,7 +1163,7 @@ void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1103 1163 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1104 1164 }
1105 1165 else {
1106   - tcg_gen_qemu_ld32s(dst, addr, mem_index);
  1166 + tcg_gen_qemu_ld32u(dst, addr, mem_index);
1107 1167 }
1108 1168 }
1109 1169  
... ... @@ -1112,8 +1172,6 @@ void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1112 1172 {
1113 1173 int mem_index = cpu_mmu_index(dc->env);
1114 1174  
1115   - cris_evaluate_flags(dc);
1116   -
1117 1175 /* Remember, operands are flipped. CRIS has reversed order. */
1118 1176 if (size == 1)
1119 1177 tcg_gen_qemu_st8(val, addr, mem_index);
... ... @@ -1129,7 +1187,7 @@ static inline void t_gen_sext(TCGv d, TCGv s, int size)
1129 1187 tcg_gen_ext8s_i32(d, s);
1130 1188 else if (size == 2)
1131 1189 tcg_gen_ext16s_i32(d, s);
1132   - else
  1190 + else if(d != s)
1133 1191 tcg_gen_mov_tl(d, s);
1134 1192 }
1135 1193  
... ... @@ -1139,7 +1197,7 @@ static inline void t_gen_zext(TCGv d, TCGv s, int size)
1139 1197 tcg_gen_ext8u_i32(d, s);
1140 1198 else if (size == 2)
1141 1199 tcg_gen_ext16u_i32(d, s);
1142   - else
  1200 + else if (d != s)
1143 1201 tcg_gen_mov_tl(d, s);
1144 1202 }
1145 1203  
... ... @@ -1158,12 +1216,12 @@ static char memsize_char(int size)
1158 1216 }
1159 1217 #endif
1160 1218  
1161   -static unsigned int memsize_z(DisasContext *dc)
  1219 +static inline unsigned int memsize_z(DisasContext *dc)
1162 1220 {
1163 1221 return dc->zsize + 1;
1164 1222 }
1165 1223  
1166   -static unsigned int memsize_zz(DisasContext *dc)
  1224 +static inline unsigned int memsize_zz(DisasContext *dc)
1167 1225 {
1168 1226 switch (dc->zzsize)
1169 1227 {
... ... @@ -1180,13 +1238,13 @@ static inline void do_postinc (DisasContext *dc, int size)
1180 1238 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1181 1239 }
1182 1240  
1183   -static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1184   - int size, int s_ext)
  1241 +static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
  1242 + int size, int s_ext, TCGv dst)
1185 1243 {
1186 1244 if (s_ext)
1187   - t_gen_sext(cpu_T[1], cpu_R[rs], size);
  1245 + t_gen_sext(dst, cpu_R[rs], size);
1188 1246 else
1189   - t_gen_zext(cpu_T[1], cpu_R[rs], size);
  1247 + t_gen_zext(dst, cpu_R[rs], size);
1190 1248 }
1191 1249  
1192 1250 /* Prepare T0 and T1 for a register alu operation.
... ... @@ -1195,7 +1253,7 @@ static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1195 1253 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1196 1254 int size, int s_ext)
1197 1255 {
1198   - dec_prep_move_r(dc, rs, rd, size, s_ext);
  1256 + dec_prep_move_r(dc, rs, rd, size, s_ext, cpu_T[1]);
1199 1257  
1200 1258 if (s_ext)
1201 1259 t_gen_sext(cpu_T[0], cpu_R[rd], size);
... ... @@ -1203,7 +1261,8 @@ static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1203 1261 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1204 1262 }
1205 1263  
1206   -static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize)
  1264 +static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
  1265 + TCGv dst)
1207 1266 {
1208 1267 unsigned int rs, rd;
1209 1268 uint32_t imm;
... ... @@ -1237,14 +1296,15 @@ static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize)
1237 1296  
1238 1297 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1239 1298 imm, rd, s_ext, memsize));
1240   - tcg_gen_movi_tl(cpu_T[1], imm);
  1299 + tcg_gen_movi_tl(dst, imm);
1241 1300 dc->postinc = 0;
1242 1301 } else {
1243   - gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
  1302 + cris_flush_cc_state(dc);
  1303 + gen_load(dc, dst, cpu_R[rs], memsize, 0);
1244 1304 if (s_ext)
1245   - t_gen_sext(cpu_T[1], cpu_T[1], memsize);
  1305 + t_gen_sext(dst, dst, memsize);
1246 1306 else
1247   - t_gen_zext(cpu_T[1], cpu_T[1], memsize);
  1307 + t_gen_zext(dst, dst, memsize);
1248 1308 }
1249 1309 return insn_len;
1250 1310 }
... ... @@ -1256,7 +1316,7 @@ static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1256 1316 {
1257 1317 int insn_len;
1258 1318  
1259   - insn_len = dec_prep_move_m(dc, s_ext, memsize);
  1319 + insn_len = dec_prep_move_m(dc, s_ext, memsize, cpu_T[1]);
1260 1320  
1261 1321 /* put dest in T0. */
1262 1322 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
... ... @@ -1317,10 +1377,9 @@ static unsigned int dec_addq(DisasContext *dc)
1317 1377 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1318 1378  
1319 1379 cris_cc_mask(dc, CC_MASK_NZVC);
1320   - /* Fetch register operand, */
1321   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1322   - tcg_gen_movi_tl(cpu_T[1], dc->op1);
1323   - crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
  1380 +
  1381 + cris_alu(dc, CC_OP_ADD,
  1382 + cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1324 1383 return 2;
1325 1384 }
1326 1385 static unsigned int dec_moveq(DisasContext *dc)
... ... @@ -1341,10 +1400,8 @@ static unsigned int dec_subq(DisasContext *dc)
1341 1400 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1342 1401  
1343 1402 cris_cc_mask(dc, CC_MASK_NZVC);
1344   - /* Fetch register operand, */
1345   - tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
1346   - tcg_gen_movi_tl(cpu_T[1], dc->op1);
1347   - crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
  1403 + cris_alu(dc, CC_OP_SUB,
  1404 + cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1348 1405 return 2;
1349 1406 }
1350 1407 static unsigned int dec_cmpq(DisasContext *dc)
... ... @@ -1355,9 +1412,9 @@ static unsigned int dec_cmpq(DisasContext *dc)
1355 1412  
1356 1413 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1357 1414 cris_cc_mask(dc, CC_MASK_NZVC);
1358   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1359   - tcg_gen_movi_tl(cpu_T[1], imm);
1360   - crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
  1415 +
  1416 + cris_alu(dc, CC_OP_CMP,
  1417 + cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1361 1418 return 2;
1362 1419 }
1363 1420 static unsigned int dec_andq(DisasContext *dc)
... ... @@ -1368,9 +1425,9 @@ static unsigned int dec_andq(DisasContext *dc)
1368 1425  
1369 1426 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1370 1427 cris_cc_mask(dc, CC_MASK_NZ);
1371   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1372   - tcg_gen_movi_tl(cpu_T[1], imm);
1373   - crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
  1428 +
  1429 + cris_alu(dc, CC_OP_AND,
  1430 + cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1374 1431 return 2;
1375 1432 }
1376 1433 static unsigned int dec_orq(DisasContext *dc)
... ... @@ -1380,9 +1437,9 @@ static unsigned int dec_orq(DisasContext *dc)
1380 1437 imm = sign_extend(dc->op1, 5);
1381 1438 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1382 1439 cris_cc_mask(dc, CC_MASK_NZ);
1383   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1384   - tcg_gen_movi_tl(cpu_T[1], imm);
1385   - crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
  1440 +
  1441 + cris_alu(dc, CC_OP_OR,
  1442 + cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1386 1443 return 2;
1387 1444 }
1388 1445 static unsigned int dec_btstq(DisasContext *dc)
... ... @@ -1391,13 +1448,13 @@ static unsigned int dec_btstq(DisasContext *dc)
1391 1448 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1392 1449  
1393 1450 cris_cc_mask(dc, CC_MASK_NZ);
1394   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1395   - tcg_gen_movi_tl(cpu_T[1], dc->op1);
1396   - crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1397 1451  
  1452 + t_gen_mov_TN_reg(cpu_T[0], dc->op2);
  1453 + cris_alu(dc, CC_OP_BTST,
  1454 + cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1398 1455 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1399 1456 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1400   - dc->flags_live = 1;
  1457 + dc->flags_uptodate = 1;
1401 1458 return 2;
1402 1459 }
1403 1460 static unsigned int dec_asrq(DisasContext *dc)
... ... @@ -1405,9 +1462,10 @@ static unsigned int dec_asrq(DisasContext *dc)
1405 1462 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1406 1463 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1407 1464 cris_cc_mask(dc, CC_MASK_NZ);
1408   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1409   - tcg_gen_movi_tl(cpu_T[1], dc->op1);
1410   - crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
  1465 +
  1466 + cris_alu(dc, CC_OP_ASR,
  1467 + cpu_R[dc->op2],
  1468 + cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1411 1469 return 2;
1412 1470 }
1413 1471 static unsigned int dec_lslq(DisasContext *dc)
... ... @@ -1416,9 +1474,10 @@ static unsigned int dec_lslq(DisasContext *dc)
1416 1474 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1417 1475  
1418 1476 cris_cc_mask(dc, CC_MASK_NZ);
1419   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1420   - tcg_gen_movi_tl(cpu_T[1], dc->op1);
1421   - crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
  1477 +
  1478 + cris_alu(dc, CC_OP_LSL,
  1479 + cpu_R[dc->op2],
  1480 + cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1422 1481 return 2;
1423 1482 }
1424 1483 static unsigned int dec_lsrq(DisasContext *dc)
... ... @@ -1427,9 +1486,10 @@ static unsigned int dec_lsrq(DisasContext *dc)
1427 1486 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1428 1487  
1429 1488 cris_cc_mask(dc, CC_MASK_NZ);
1430   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1431   - tcg_gen_movi_tl(cpu_T[1], dc->op1);
1432   - crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
  1489 +
  1490 + cris_alu(dc, CC_OP_LSR,
  1491 + cpu_R[dc->op2],
  1492 + cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1433 1493 return 2;
1434 1494 }
1435 1495  
... ... @@ -1441,8 +1501,19 @@ static unsigned int dec_move_r(DisasContext *dc)
1441 1501 memsize_char(size), dc->op1, dc->op2));
1442 1502  
1443 1503 cris_cc_mask(dc, CC_MASK_NZ);
1444   - dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1445   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
  1504 + if (size == 4) {
  1505 + dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
  1506 + cris_cc_mask(dc, CC_MASK_NZ);
  1507 + cris_update_cc_op(dc, CC_OP_MOVE, 4);
  1508 + cris_update_cc_x(dc);
  1509 + cris_update_result(dc, cpu_R[dc->op2]);
  1510 + }
  1511 + else {
  1512 + dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
  1513 + cris_alu(dc, CC_OP_MOVE,
  1514 + cpu_R[dc->op2],
  1515 + cpu_R[dc->op2], cpu_T[1], size);
  1516 + }
1446 1517 return 2;
1447 1518 }
1448 1519  
... ... @@ -1480,7 +1551,10 @@ static unsigned int dec_and_r(DisasContext *dc)
1480 1551 memsize_char(size), dc->op1, dc->op2));
1481 1552 cris_cc_mask(dc, CC_MASK_NZ);
1482 1553 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1483   - crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
  1554 +
  1555 + cris_alu(dc, CC_OP_AND,
  1556 + cpu_R[dc->op2],
  1557 + cpu_R[dc->op2], cpu_T[1], size);
1484 1558 return 2;
1485 1559 }
1486 1560  
... ... @@ -1490,7 +1564,8 @@ static unsigned int dec_lz_r(DisasContext *dc)
1490 1564 dc->op1, dc->op2));
1491 1565 cris_cc_mask(dc, CC_MASK_NZ);
1492 1566 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1493   - crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
  1567 + cris_alu(dc, CC_OP_LZ,
  1568 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1494 1569 return 2;
1495 1570 }
1496 1571  
... ... @@ -1503,7 +1578,9 @@ static unsigned int dec_lsl_r(DisasContext *dc)
1503 1578 cris_cc_mask(dc, CC_MASK_NZ);
1504 1579 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1505 1580 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1506   - crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
  1581 +
  1582 + cris_alu(dc, CC_OP_LSL,
  1583 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1507 1584 return 2;
1508 1585 }
1509 1586  
... ... @@ -1516,7 +1593,9 @@ static unsigned int dec_lsr_r(DisasContext *dc)
1516 1593 cris_cc_mask(dc, CC_MASK_NZ);
1517 1594 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1518 1595 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1519   - crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
  1596 +
  1597 + cris_alu(dc, CC_OP_LSR,
  1598 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1520 1599 return 2;
1521 1600 }
1522 1601  
... ... @@ -1529,7 +1608,9 @@ static unsigned int dec_asr_r(DisasContext *dc)
1529 1608 cris_cc_mask(dc, CC_MASK_NZ);
1530 1609 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1531 1610 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1532   - crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
  1611 +
  1612 + cris_alu(dc, CC_OP_ASR,
  1613 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1533 1614 return 2;
1534 1615 }
1535 1616  
... ... @@ -1541,8 +1622,9 @@ static unsigned int dec_muls_r(DisasContext *dc)
1541 1622 memsize_char(size), dc->op1, dc->op2));
1542 1623 cris_cc_mask(dc, CC_MASK_NZV);
1543 1624 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1544   - t_gen_sext(cpu_T[0], cpu_T[0], size);
1545   - crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
  1625 +
  1626 + cris_alu(dc, CC_OP_MULS,
  1627 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1546 1628 return 2;
1547 1629 }
1548 1630  
... ... @@ -1554,8 +1636,9 @@ static unsigned int dec_mulu_r(DisasContext *dc)
1554 1636 memsize_char(size), dc->op1, dc->op2));
1555 1637 cris_cc_mask(dc, CC_MASK_NZV);
1556 1638 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1557   - t_gen_zext(cpu_T[0], cpu_T[0], size);
1558   - crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
  1639 +
  1640 + cris_alu(dc, CC_OP_MULU,
  1641 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1559 1642 return 2;
1560 1643 }
1561 1644  
... ... @@ -1564,9 +1647,8 @@ static unsigned int dec_dstep_r(DisasContext *dc)
1564 1647 {
1565 1648 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1566 1649 cris_cc_mask(dc, CC_MASK_NZ);
1567   - t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1568   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1569   - crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
  1650 + cris_alu(dc, CC_OP_DSTEP,
  1651 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1570 1652 return 2;
1571 1653 }
1572 1654  
... ... @@ -1578,7 +1660,9 @@ static unsigned int dec_xor_r(DisasContext *dc)
1578 1660 BUG_ON(size != 4); /* xor is dword. */
1579 1661 cris_cc_mask(dc, CC_MASK_NZ);
1580 1662 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1581   - crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
  1663 +
  1664 + cris_alu(dc, CC_OP_XOR,
  1665 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1582 1666 return 2;
1583 1667 }
1584 1668  
... ... @@ -1588,11 +1672,9 @@ static unsigned int dec_bound_r(DisasContext *dc)
1588 1672 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1589 1673 memsize_char(size), dc->op1, dc->op2));
1590 1674 cris_cc_mask(dc, CC_MASK_NZ);
1591   - /* TODO: needs optmimization. */
1592   - dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1593   - /* rd should be 4. */
1594   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1595   - crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
  1675 + dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
  1676 + cris_alu(dc, CC_OP_BOUND,
  1677 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1596 1678 return 2;
1597 1679 }
1598 1680  
... ... @@ -1603,7 +1685,9 @@ static unsigned int dec_cmp_r(DisasContext *dc)
1603 1685 memsize_char(size), dc->op1, dc->op2));
1604 1686 cris_cc_mask(dc, CC_MASK_NZVC);
1605 1687 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1606   - crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
  1688 +
  1689 + cris_alu(dc, CC_OP_CMP,
  1690 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1607 1691 return 2;
1608 1692 }
1609 1693  
... ... @@ -1614,14 +1698,15 @@ static unsigned int dec_abs_r(DisasContext *dc)
1614 1698 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1615 1699 dc->op1, dc->op2));
1616 1700 cris_cc_mask(dc, CC_MASK_NZ);
1617   - dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
  1701 + dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0, cpu_T[1]);
1618 1702  
1619 1703 /* TODO: consider a branch free approach. */
1620 1704 l1 = gen_new_label();
1621 1705 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_T[1], 0, l1);
1622 1706 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
1623 1707 gen_set_label(l1);
1624   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
  1708 + cris_alu(dc, CC_OP_MOVE,
  1709 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1625 1710 return 2;
1626 1711 }
1627 1712  
... ... @@ -1632,7 +1717,9 @@ static unsigned int dec_add_r(DisasContext *dc)
1632 1717 memsize_char(size), dc->op1, dc->op2));
1633 1718 cris_cc_mask(dc, CC_MASK_NZVC);
1634 1719 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1635   - crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
  1720 +
  1721 + cris_alu(dc, CC_OP_ADD,
  1722 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1636 1723 return 2;
1637 1724 }
1638 1725  
... ... @@ -1643,7 +1730,8 @@ static unsigned int dec_addc_r(DisasContext *dc)
1643 1730 cris_evaluate_flags(dc);
1644 1731 cris_cc_mask(dc, CC_MASK_NZVC);
1645 1732 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1646   - crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
  1733 + cris_alu(dc, CC_OP_ADDC,
  1734 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1647 1735 return 2;
1648 1736 }
1649 1737  
... ... @@ -1653,9 +1741,8 @@ static unsigned int dec_mcp_r(DisasContext *dc)
1653 1741 dc->op2, dc->op1));
1654 1742 cris_evaluate_flags(dc);
1655 1743 cris_cc_mask(dc, CC_MASK_RNZV);
1656   - t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1657   - t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1658   - crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
  1744 + cris_alu(dc, CC_OP_MCP,
  1745 + cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1659 1746 return 2;
1660 1747 }
1661 1748  
... ... @@ -1693,8 +1780,9 @@ static unsigned int dec_swap_r(DisasContext *dc)
1693 1780 t_gen_swapb(cpu_T[0], cpu_T[0]);
1694 1781 if (dc->op2 & 1)
1695 1782 t_gen_swapr(cpu_T[0], cpu_T[0]);
1696   - tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1697   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
  1783 + cris_alu(dc, CC_OP_MOVE,
  1784 + cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0], 4);
  1785 +
1698 1786 return 2;
1699 1787 }
1700 1788  
... ... @@ -1705,7 +1793,9 @@ static unsigned int dec_or_r(DisasContext *dc)
1705 1793 memsize_char(size), dc->op1, dc->op2));
1706 1794 cris_cc_mask(dc, CC_MASK_NZ);
1707 1795 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1708   - crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
  1796 +
  1797 + cris_alu(dc, CC_OP_OR,
  1798 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1709 1799 return 2;
1710 1800 }
1711 1801  
... ... @@ -1714,10 +1804,8 @@ static unsigned int dec_addi_r(DisasContext *dc)
1714 1804 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1715 1805 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1716 1806 cris_cc_mask(dc, 0);
1717   - dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1718   - t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1719   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1720   - t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
  1807 + tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
  1808 + tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0]);
1721 1809 return 2;
1722 1810 }
1723 1811  
... ... @@ -1726,11 +1814,8 @@ static unsigned int dec_addi_acr(DisasContext *dc)
1726 1814 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1727 1815 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1728 1816 cris_cc_mask(dc, 0);
1729   - dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1730   - t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1731   -
1732   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1733   - t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
  1817 + tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
  1818 + tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], cpu_T[0]);
1734 1819 return 2;
1735 1820 }
1736 1821  
... ... @@ -1741,7 +1826,9 @@ static unsigned int dec_neg_r(DisasContext *dc)
1741 1826 memsize_char(size), dc->op1, dc->op2));
1742 1827 cris_cc_mask(dc, CC_MASK_NZVC);
1743 1828 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1744   - crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
  1829 +
  1830 + cris_alu(dc, CC_OP_NEG,
  1831 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1745 1832 return 2;
1746 1833 }
1747 1834  
... ... @@ -1751,11 +1838,12 @@ static unsigned int dec_btst_r(DisasContext *dc)
1751 1838 dc->op1, dc->op2));
1752 1839 cris_cc_mask(dc, CC_MASK_NZ);
1753 1840 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1754   - crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1755 1841  
  1842 + cris_alu(dc, CC_OP_BTST,
  1843 + cpu_T[0], cpu_T[0], cpu_T[1], 4);
1756 1844 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1757 1845 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
1758   - dc->flags_live = 1;
  1846 + dc->flags_uptodate = 1;
1759 1847 return 2;
1760 1848 }
1761 1849  
... ... @@ -1766,7 +1854,8 @@ static unsigned int dec_sub_r(DisasContext *dc)
1766 1854 memsize_char(size), dc->op1, dc->op2));
1767 1855 cris_cc_mask(dc, CC_MASK_NZVC);
1768 1856 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1769   - crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
  1857 + cris_alu(dc, CC_OP_SUB,
  1858 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
1770 1859 return 2;
1771 1860 }
1772 1861  
... ... @@ -1779,8 +1868,9 @@ static unsigned int dec_movu_r(DisasContext *dc)
1779 1868 dc->op1, dc->op2));
1780 1869  
1781 1870 cris_cc_mask(dc, CC_MASK_NZ);
1782   - dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1783   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
  1871 + dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
  1872 + cris_alu(dc, CC_OP_MOVE,
  1873 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1784 1874 return 2;
1785 1875 }
1786 1876  
... ... @@ -1795,8 +1885,9 @@ static unsigned int dec_movs_r(DisasContext *dc)
1795 1885 cris_cc_mask(dc, CC_MASK_NZ);
1796 1886 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1797 1887 /* Size can only be qi or hi. */
1798   - t_gen_sext(cpu_T[1], cpu_T[0], size);
1799   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
  1888 + t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
  1889 + cris_alu(dc, CC_OP_MOVE,
  1890 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
1800 1891 return 2;
1801 1892 }
1802 1893  
... ... @@ -1809,11 +1900,10 @@ static unsigned int dec_addu_r(DisasContext *dc)
1809 1900 dc->op1, dc->op2));
1810 1901  
1811 1902 cris_cc_mask(dc, CC_MASK_NZVC);
1812   - t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1813 1903 /* Size can only be qi or hi. */
1814   - t_gen_zext(cpu_T[1], cpu_T[1], size);
1815   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1816   - crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
  1904 + t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
  1905 + cris_alu(dc, CC_OP_ADD,
  1906 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1817 1907 return 2;
1818 1908 }
1819 1909  
... ... @@ -1826,12 +1916,10 @@ static unsigned int dec_adds_r(DisasContext *dc)
1826 1916 dc->op1, dc->op2));
1827 1917  
1828 1918 cris_cc_mask(dc, CC_MASK_NZVC);
1829   - t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1830 1919 /* Size can only be qi or hi. */
1831   - t_gen_sext(cpu_T[1], cpu_T[1], size);
1832   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1833   -
1834   - crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
  1920 + t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
  1921 + cris_alu(dc, CC_OP_ADD,
  1922 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1835 1923 return 2;
1836 1924 }
1837 1925  
... ... @@ -1844,11 +1932,10 @@ static unsigned int dec_subu_r(DisasContext *dc)
1844 1932 dc->op1, dc->op2));
1845 1933  
1846 1934 cris_cc_mask(dc, CC_MASK_NZVC);
1847   - t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1848 1935 /* Size can only be qi or hi. */
1849   - t_gen_zext(cpu_T[1], cpu_T[1], size);
1850   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1851   - crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
  1936 + t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
  1937 + cris_alu(dc, CC_OP_SUB,
  1938 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1852 1939 return 2;
1853 1940 }
1854 1941  
... ... @@ -1861,11 +1948,10 @@ static unsigned int dec_subs_r(DisasContext *dc)
1861 1948 dc->op1, dc->op2));
1862 1949  
1863 1950 cris_cc_mask(dc, CC_MASK_NZVC);
1864   - t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1865 1951 /* Size can only be qi or hi. */
1866   - t_gen_sext(cpu_T[1], cpu_T[1], size);
1867   - t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1868   - crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
  1952 + t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
  1953 + cris_alu(dc, CC_OP_SUB,
  1954 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
1869 1955 return 2;
1870 1956 }
1871 1957  
... ... @@ -1879,6 +1965,7 @@ static unsigned int dec_setclrf(DisasContext *dc)
1879 1965 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1880 1966 if (set && flags == 0) {
1881 1967 DIS(fprintf (logfile, "nop\n"));
  1968 + return 2;
1882 1969 } else if (!set && (flags & 0x20)) {
1883 1970 DIS(fprintf (logfile, "di\n"));
1884 1971 }
... ... @@ -1889,13 +1976,16 @@ static unsigned int dec_setclrf(DisasContext *dc)
1889 1976 }
1890 1977  
1891 1978 if (set && (flags & X_FLAG)) {
1892   - dc->flagx_live = 1;
1893   - dc->flags_x = 1;
  1979 + dc->flagx_known = 1;
  1980 + dc->flags_x = X_FLAG;
  1981 + } else {
  1982 + dc->flagx_known = 0;
1894 1983 }
1895 1984  
1896 1985 /* Simply decode the flags. */
1897 1986 cris_evaluate_flags (dc);
1898 1987 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
  1988 + cris_update_cc_x(dc);
1899 1989 tcg_gen_movi_tl(cc_op, dc->cc_op);
1900 1990  
1901 1991 if (set) {
... ... @@ -1910,7 +2000,7 @@ static unsigned int dec_setclrf(DisasContext *dc)
1910 2000 else
1911 2001 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
1912 2002  
1913   - dc->flags_live = 1;
  2003 + dc->flags_uptodate = 1;
1914 2004 dc->clear_x = 0;
1915 2005 return 2;
1916 2006 }
... ... @@ -1953,7 +2043,7 @@ static unsigned int dec_move_rp(DisasContext *dc)
1953 2043 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
1954 2044 if (dc->op2 == PR_CCS) {
1955 2045 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1956   - dc->flags_live = 1;
  2046 + dc->flags_uptodate = 1;
1957 2047 }
1958 2048 return 2;
1959 2049 }
... ... @@ -1970,7 +2060,9 @@ static unsigned int dec_move_pr(DisasContext *dc)
1970 2060 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1971 2061 } else
1972 2062 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1973   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
  2063 + cris_alu(dc, CC_OP_MOVE,
  2064 + cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[1],
  2065 + preg_sizes[dc->op2]);
1974 2066 return 2;
1975 2067 }
1976 2068  
... ... @@ -1983,9 +2075,19 @@ static unsigned int dec_move_mr(DisasContext *dc)
1983 2075 dc->op1, dc->postinc ? "+]" : "]",
1984 2076 dc->op2));
1985 2077  
1986   - insn_len = dec_prep_move_m(dc, 0, memsize);
1987   - cris_cc_mask(dc, CC_MASK_NZ);
1988   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
  2078 + if (memsize == 4) {
  2079 + insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
  2080 + cris_cc_mask(dc, CC_MASK_NZ);
  2081 + cris_update_cc_op(dc, CC_OP_MOVE, 4);
  2082 + cris_update_cc_x(dc);
  2083 + cris_update_result(dc, cpu_R[dc->op2]);
  2084 + }
  2085 + else {
  2086 + insn_len = dec_prep_move_m(dc, 0, memsize, cpu_T[1]);
  2087 + cris_cc_mask(dc, CC_MASK_NZ);
  2088 + cris_alu(dc, CC_OP_MOVE,
  2089 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], memsize);
  2090 + }
1989 2091 do_postinc(dc, memsize);
1990 2092 return insn_len;
1991 2093 }
... ... @@ -2002,7 +2104,8 @@ static unsigned int dec_movs_m(DisasContext *dc)
2002 2104 /* sign extend. */
2003 2105 insn_len = dec_prep_alu_m(dc, 1, memsize);
2004 2106 cris_cc_mask(dc, CC_MASK_NZ);
2005   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
  2107 + cris_alu(dc, CC_OP_MOVE,
  2108 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2006 2109 do_postinc(dc, memsize);
2007 2110 return insn_len;
2008 2111 }
... ... @@ -2019,7 +2122,8 @@ static unsigned int dec_addu_m(DisasContext *dc)
2019 2122 /* sign extend. */
2020 2123 insn_len = dec_prep_alu_m(dc, 0, memsize);
2021 2124 cris_cc_mask(dc, CC_MASK_NZVC);
2022   - crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
  2125 + cris_alu(dc, CC_OP_ADD,
  2126 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2023 2127 do_postinc(dc, memsize);
2024 2128 return insn_len;
2025 2129 }
... ... @@ -2036,7 +2140,8 @@ static unsigned int dec_adds_m(DisasContext *dc)
2036 2140 /* sign extend. */
2037 2141 insn_len = dec_prep_alu_m(dc, 1, memsize);
2038 2142 cris_cc_mask(dc, CC_MASK_NZVC);
2039   - crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
  2143 + cris_alu(dc, CC_OP_ADD,
  2144 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2040 2145 do_postinc(dc, memsize);
2041 2146 return insn_len;
2042 2147 }
... ... @@ -2053,7 +2158,8 @@ static unsigned int dec_subu_m(DisasContext *dc)
2053 2158 /* sign extend. */
2054 2159 insn_len = dec_prep_alu_m(dc, 0, memsize);
2055 2160 cris_cc_mask(dc, CC_MASK_NZVC);
2056   - crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
  2161 + cris_alu(dc, CC_OP_SUB,
  2162 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2057 2163 do_postinc(dc, memsize);
2058 2164 return insn_len;
2059 2165 }
... ... @@ -2070,7 +2176,8 @@ static unsigned int dec_subs_m(DisasContext *dc)
2070 2176 /* sign extend. */
2071 2177 insn_len = dec_prep_alu_m(dc, 1, memsize);
2072 2178 cris_cc_mask(dc, CC_MASK_NZVC);
2073   - crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
  2179 + cris_alu(dc, CC_OP_SUB,
  2180 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2074 2181 do_postinc(dc, memsize);
2075 2182 return insn_len;
2076 2183 }
... ... @@ -2087,7 +2194,8 @@ static unsigned int dec_movu_m(DisasContext *dc)
2087 2194  
2088 2195 insn_len = dec_prep_alu_m(dc, 0, memsize);
2089 2196 cris_cc_mask(dc, CC_MASK_NZ);
2090   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
  2197 + cris_alu(dc, CC_OP_MOVE,
  2198 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2091 2199 do_postinc(dc, memsize);
2092 2200 return insn_len;
2093 2201 }
... ... @@ -2103,7 +2211,8 @@ static unsigned int dec_cmpu_m(DisasContext *dc)
2103 2211  
2104 2212 insn_len = dec_prep_alu_m(dc, 0, memsize);
2105 2213 cris_cc_mask(dc, CC_MASK_NZVC);
2106   - crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
  2214 + cris_alu(dc, CC_OP_CMP,
  2215 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
2107 2216 do_postinc(dc, memsize);
2108 2217 return insn_len;
2109 2218 }
... ... @@ -2119,7 +2228,9 @@ static unsigned int dec_cmps_m(DisasContext *dc)
2119 2228  
2120 2229 insn_len = dec_prep_alu_m(dc, 1, memsize);
2121 2230 cris_cc_mask(dc, CC_MASK_NZVC);
2122   - crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
  2231 + cris_alu(dc, CC_OP_CMP,
  2232 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
  2233 + memsize_zz(dc));
2123 2234 do_postinc(dc, memsize);
2124 2235 return insn_len;
2125 2236 }
... ... @@ -2135,7 +2246,9 @@ static unsigned int dec_cmp_m(DisasContext *dc)
2135 2246  
2136 2247 insn_len = dec_prep_alu_m(dc, 0, memsize);
2137 2248 cris_cc_mask(dc, CC_MASK_NZVC);
2138   - crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
  2249 + cris_alu(dc, CC_OP_CMP,
  2250 + cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
  2251 + memsize_zz(dc));
2139 2252 do_postinc(dc, memsize);
2140 2253 return insn_len;
2141 2254 }
... ... @@ -2155,9 +2268,9 @@ static unsigned int dec_test_m(DisasContext *dc)
2155 2268 cris_cc_mask(dc, CC_MASK_NZ);
2156 2269 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2157 2270  
2158   - tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2159   - tcg_gen_movi_tl(cpu_T[1], 0);
2160   - crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
  2271 + cris_alu(dc, CC_OP_CMP,
  2272 + cpu_R[dc->op2], cpu_T[1], tcg_const_tl(0),
  2273 + memsize_zz(dc));
2161 2274 do_postinc(dc, memsize);
2162 2275 return insn_len;
2163 2276 }
... ... @@ -2173,7 +2286,9 @@ static unsigned int dec_and_m(DisasContext *dc)
2173 2286  
2174 2287 insn_len = dec_prep_alu_m(dc, 0, memsize);
2175 2288 cris_cc_mask(dc, CC_MASK_NZ);
2176   - crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
  2289 + cris_alu(dc, CC_OP_AND,
  2290 + cpu_R[dc->op2], cpu_T[0], cpu_T[1],
  2291 + memsize_zz(dc));
2177 2292 do_postinc(dc, memsize);
2178 2293 return insn_len;
2179 2294 }
... ... @@ -2189,7 +2304,9 @@ static unsigned int dec_add_m(DisasContext *dc)
2189 2304  
2190 2305 insn_len = dec_prep_alu_m(dc, 0, memsize);
2191 2306 cris_cc_mask(dc, CC_MASK_NZVC);
2192   - crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
  2307 + cris_alu(dc, CC_OP_ADD,
  2308 + cpu_R[dc->op2], cpu_T[0], cpu_T[1],
  2309 + memsize_zz(dc));
2193 2310 do_postinc(dc, memsize);
2194 2311 return insn_len;
2195 2312 }
... ... @@ -2205,7 +2322,8 @@ static unsigned int dec_addo_m(DisasContext *dc)
2205 2322  
2206 2323 insn_len = dec_prep_alu_m(dc, 1, memsize);
2207 2324 cris_cc_mask(dc, 0);
2208   - crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
  2325 + cris_alu(dc, CC_OP_ADD,
  2326 + cpu_R[R_ACR], cpu_T[0], cpu_T[1], 4);
2209 2327 do_postinc(dc, memsize);
2210 2328 return insn_len;
2211 2329 }
... ... @@ -2221,7 +2339,8 @@ static unsigned int dec_bound_m(DisasContext *dc)
2221 2339  
2222 2340 insn_len = dec_prep_alu_m(dc, 0, memsize);
2223 2341 cris_cc_mask(dc, CC_MASK_NZ);
2224   - crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
  2342 + cris_alu(dc, CC_OP_BOUND,
  2343 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2225 2344 do_postinc(dc, memsize);
2226 2345 return insn_len;
2227 2346 }
... ... @@ -2236,7 +2355,8 @@ static unsigned int dec_addc_mr(DisasContext *dc)
2236 2355 cris_evaluate_flags(dc);
2237 2356 insn_len = dec_prep_alu_m(dc, 0, 4);
2238 2357 cris_cc_mask(dc, CC_MASK_NZVC);
2239   - crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
  2358 + cris_alu(dc, CC_OP_ADDC,
  2359 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
2240 2360 do_postinc(dc, 4);
2241 2361 return insn_len;
2242 2362 }
... ... @@ -2252,7 +2372,8 @@ static unsigned int dec_sub_m(DisasContext *dc)
2252 2372  
2253 2373 insn_len = dec_prep_alu_m(dc, 0, memsize);
2254 2374 cris_cc_mask(dc, CC_MASK_NZVC);
2255   - crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
  2375 + cris_alu(dc, CC_OP_SUB,
  2376 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize);
2256 2377 do_postinc(dc, memsize);
2257 2378 return insn_len;
2258 2379 }
... ... @@ -2268,7 +2389,8 @@ static unsigned int dec_or_m(DisasContext *dc)
2268 2389  
2269 2390 insn_len = dec_prep_alu_m(dc, 0, memsize);
2270 2391 cris_cc_mask(dc, CC_MASK_NZ);
2271   - crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
  2392 + cris_alu(dc, CC_OP_OR,
  2393 + cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize_zz(dc));
2272 2394 do_postinc(dc, memsize);
2273 2395 return insn_len;
2274 2396 }
... ... @@ -2316,6 +2438,7 @@ static unsigned int dec_move_pm(DisasContext *dc)
2316 2438 if (dc->op2 == PR_CCS)
2317 2439 cris_evaluate_flags(dc);
2318 2440 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
  2441 + cris_flush_cc_state(dc);
2319 2442 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2320 2443  
2321 2444 cris_cc_mask(dc, 0);
... ... @@ -2333,6 +2456,7 @@ static unsigned int dec_movem_mr(DisasContext *dc)
2333 2456 dc->postinc ? "+]" : "]", dc->op2));
2334 2457  
2335 2458 /* fetch the address into T0 and T1. */
  2459 + cris_flush_cc_state(dc);
2336 2460 for (i = 0; i <= dc->op2; i++) {
2337 2461 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
2338 2462 /* Perform the load onto regnum i. Always dword wide. */
... ... @@ -2342,7 +2466,7 @@ static unsigned int dec_movem_mr(DisasContext *dc)
2342 2466  
2343 2467 for (i = 0; i <= dc->op2; i++) {
2344 2468 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
2345   - tcg_gen_discard_tl(tmp[i]);
  2469 + tcg_temp_free(tmp[i]);
2346 2470 }
2347 2471  
2348 2472 /* writeback the updated pointer value. */
... ... @@ -2356,20 +2480,27 @@ static unsigned int dec_movem_mr(DisasContext *dc)
2356 2480  
2357 2481 static unsigned int dec_movem_rm(DisasContext *dc)
2358 2482 {
  2483 + TCGv tmp;
2359 2484 int i;
2360 2485  
2361 2486 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2362 2487 dc->postinc ? "+]" : "]"));
2363 2488  
  2489 + cris_flush_cc_state(dc);
  2490 +
  2491 + tmp = tcg_temp_new(TCG_TYPE_TL);
  2492 + tcg_gen_movi_tl(tmp, 4);
  2493 + tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op1]);
2364 2494 for (i = 0; i <= dc->op2; i++) {
2365 2495 /* Displace addr. */
2366   - tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2367 2496 /* Perform the store. */
2368 2497 gen_store(dc, cpu_T[0], cpu_R[i], 4);
  2498 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], tmp);
2369 2499 }
2370 2500 if (dc->postinc)
2371   - tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
  2501 + tcg_gen_mov_tl(cpu_R[dc->op1], cpu_T[0]);
2372 2502 cris_cc_mask(dc, 0);
  2503 + tcg_temp_free(tmp);
2373 2504 return 2;
2374 2505 }
2375 2506  
... ... @@ -2383,6 +2514,7 @@ static unsigned int dec_move_rm(DisasContext *dc)
2383 2514 memsize, dc->op2, dc->op1));
2384 2515  
2385 2516 /* prepare store. */
  2517 + cris_flush_cc_state(dc);
2386 2518 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2387 2519  
2388 2520 if (dc->postinc)
... ... @@ -2396,8 +2528,7 @@ static unsigned int dec_lapcq(DisasContext *dc)
2396 2528 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2397 2529 dc->pc + dc->op1*2, dc->op2));
2398 2530 cris_cc_mask(dc, 0);
2399   - tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
2400   - crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
  2531 + tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2401 2532 return 2;
2402 2533 }
2403 2534  
... ... @@ -2443,8 +2574,7 @@ static unsigned int dec_jas_r(DisasContext *dc)
2443 2574 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2444 2575 if (dc->op2 > 15)
2445 2576 abort();
2446   - tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
2447   - tcg_gen_mov_tl(cpu_PR[dc->op2], cpu_T[0]);
  2577 + t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2448 2578  
2449 2579 cris_prepare_dyn_jmp(dc);
2450 2580 return 2;
... ... @@ -2827,12 +2957,15 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2827 2957 dc->ppc = pc_start;
2828 2958 dc->pc = pc_start;
2829 2959 dc->singlestep_enabled = env->singlestep_enabled;
2830   - dc->flags_live = 1;
2831   - dc->flagx_live = 0;
2832   - dc->flags_x = 0;
  2960 + dc->flags_uptodate = 1;
  2961 + dc->flagx_known = 1;
  2962 + dc->flags_x = tb->flags & X_FLAG;
  2963 + dc->cc_x_uptodate = 0;
2833 2964 dc->cc_mask = 0;
2834 2965 dc->update_cc = 0;
  2966 +
2835 2967 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
  2968 + dc->cc_size_uptodate = -1;
2836 2969  
2837 2970 /* Decode TB flags. */
2838 2971 dc->user = tb->flags & U_FLAG;
... ... @@ -2841,7 +2974,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2841 2974 if (loglevel & CPU_LOG_TB_IN_ASM) {
2842 2975 fprintf(logfile,
2843 2976 "srch=%d pc=%x %x bt=%x ds=%lld ccs=%x\n"
2844   - "pid=%x usp=%x dbg=%x %x %x\n"
  2977 + "pid=%x usp=%x\n"
2845 2978 "%x.%x.%x.%x\n"
2846 2979 "%x.%x.%x.%x\n"
2847 2980 "%x.%x.%x.%x\n"
... ... @@ -2850,7 +2983,6 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2850 2983 env->btarget, tb->flags & 7,
2851 2984 env->pregs[PR_CCS],
2852 2985 env->pregs[PR_PID], env->pregs[PR_USP],
2853   - env->debug1, env->debug2, env->debug3,
2854 2986 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2855 2987 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2856 2988 env->regs[8], env->regs[9],
... ... @@ -2890,6 +3022,8 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2890 3022 }
2891 3023  
2892 3024 dc->clear_x = 1;
  3025 + if (unlikely(loglevel & CPU_LOG_TB_OP))
  3026 + tcg_gen_debug_insn_start(dc->pc);
2893 3027 insn_len = cris_decoder(dc);
2894 3028 dc->ppc = dc->pc;
2895 3029 dc->pc += insn_len;
... ... @@ -2996,12 +3130,11 @@ void cpu_dump_state (CPUState *env, FILE *f,
2996 3130 return;
2997 3131  
2998 3132 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2999   - "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
3000   - "debug=%x %x %x\n",
  3133 + "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3001 3134 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3002 3135 env->cc_op,
3003   - env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
3004   - env->debug1, env->debug2, env->debug3);
  3136 + env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
  3137 +
3005 3138  
3006 3139 for (i = 0; i < 16; i++) {
3007 3140 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
... ... @@ -3049,38 +3182,40 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
3049 3182 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3050 3183 #endif
3051 3184  
3052   - cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3185 + cc_x = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3186 + offsetof(CPUState, cc_x), "cc_x");
  3187 + cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3053 3188 offsetof(CPUState, cc_src), "cc_src");
3054   - cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3055   - offsetof(CPUState, cc_dest),
  3189 + cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3190 + offsetof(CPUState, cc_dest),
3056 3191 "cc_dest");
3057   - cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3058   - offsetof(CPUState, cc_result),
  3192 + cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3193 + offsetof(CPUState, cc_result),
3059 3194 "cc_result");
3060   - cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3195 + cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3061 3196 offsetof(CPUState, cc_op), "cc_op");
3062   - cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3063   - offsetof(CPUState, cc_size),
  3197 + cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3198 + offsetof(CPUState, cc_size),
3064 3199 "cc_size");
3065   - cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3200 + cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3066 3201 offsetof(CPUState, cc_mask),
3067 3202 "cc_mask");
3068 3203  
3069 3204 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3070   - offsetof(CPUState, pc),
3071   - "pc");
3072   - env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3073   - offsetof(CPUState, btarget),
3074   - "btarget");
  3205 + offsetof(CPUState, pc),
  3206 + "pc");
  3207 + env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3208 + offsetof(CPUState, btarget),
  3209 + "btarget");
3075 3210  
3076 3211 for (i = 0; i < 16; i++) {
3077   - cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3078   - offsetof(CPUState, regs[i]),
  3212 + cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3213 + offsetof(CPUState, regs[i]),
3079 3214 regnames[i]);
3080 3215 }
3081 3216 for (i = 0; i < 16; i++) {
3082   - cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3083   - offsetof(CPUState, pregs[i]),
  3217 + cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
  3218 + offsetof(CPUState, pregs[i]),
3084 3219 pregnames[i]);
3085 3220 }
3086 3221  
... ... @@ -3089,7 +3224,6 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
3089 3224 TCG_HELPER(helper_dump);
3090 3225 TCG_HELPER(helper_dummy);
3091 3226  
3092   - TCG_HELPER(helper_tlb_flush);
3093 3227 TCG_HELPER(helper_tlb_flush_pid);
3094 3228 TCG_HELPER(helper_movl_sreg_reg);
3095 3229 TCG_HELPER(helper_movl_reg_sreg);
... ... @@ -3102,6 +3236,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
3102 3236 TCG_HELPER(helper_evaluate_flags_move_4);
3103 3237 TCG_HELPER(helper_evaluate_flags_move_2);
3104 3238 TCG_HELPER(helper_evaluate_flags);
  3239 + TCG_HELPER(helper_top_evaluate_flags);
3105 3240  
3106 3241 cpu_reset(env);
3107 3242 return env;
... ...