gwj / at91sam9263 · Commits

Commit 30898801ad8c70708ead392b243ca8bcd28ca722

Authored by ths
1 parent 20c4c97c

Switch MIPS clo/clz and the condition tests to TCG. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4507 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 4 changed files with 80 additions and 74 deletions
target-mips/helper.h
  View file @3089880
1 1 void do_raise_exception_err(int excp, int err);
2 2 void do_raise_exception(int excp);
3 3 void do_interrupt_restart (void);
  4 +
  5 +void do_clo (void);
  6 +void do_clz (void);
  7 +void do_dclo (void);
  8 +void do_dclz (void);
... ...
target-mips/op.c
  View file @3089880
... ... @@ -167,51 +167,6 @@
167 167 #undef MEMSUFFIX
168 168 #endif
169 169  
170   -/* Logical */
171   -void op_clo (void)
172   -{
173   - T0 = clo32(T0);
174   - FORCE_RET();
175   -}
176   -
177   -void op_clz (void)
178   -{
179   - T0 = clz32(T0);
180   - FORCE_RET();
181   -}
182   -
183   -#if defined(TARGET_MIPS64)
184   -
185   -#if TARGET_LONG_BITS > HOST_LONG_BITS
186   -/* Those might call libgcc functions. */
187   -void op_dclo (void)
188   -{
189   - CALL_FROM_TB0(do_dclo);
190   - FORCE_RET();
191   -}
192   -
193   -void op_dclz (void)
194   -{
195   - CALL_FROM_TB0(do_dclz);
196   - FORCE_RET();
197   -}
198   -
199   -#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
200   -
201   -void op_dclo (void)
202   -{
203   - T0 = clo64(T0);
204   - FORCE_RET();
205   -}
206   -
207   -void op_dclz (void)
208   -{
209   - T0 = clz64(T0);
210   - FORCE_RET();
211   -}
212   -#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
213   -#endif /* TARGET_MIPS64 */
214   -
215 170 /* 64 bits arithmetic */
216 171 #if TARGET_LONG_BITS > HOST_LONG_BITS
217 172 void op_mult (void)
... ... @@ -524,29 +479,6 @@ void op_movt (void)
524 479 FORCE_RET();
525 480 }
526 481  
527   -/* Tests */
528   -#define OP_COND(name, cond) \
529   -void glue(op_, name) (void) \
530   -{ \
531   - if (cond) { \
532   - T0 = 1; \
533   - } else { \
534   - T0 = 0; \
535   - } \
536   - FORCE_RET(); \
537   -}
538   -
539   -OP_COND(eq, T0 == T1);
540   -OP_COND(ne, T0 != T1);
541   -OP_COND(ge, (target_long)T0 >= (target_long)T1);
542   -OP_COND(geu, T0 >= T1);
543   -OP_COND(lt, (target_long)T0 < (target_long)T1);
544   -OP_COND(ltu, T0 < T1);
545   -OP_COND(gez, (target_long)T0 >= 0);
546   -OP_COND(gtz, (target_long)T0 > 0);
547   -OP_COND(lez, (target_long)T0 <= 0);
548   -OP_COND(ltz, (target_long)T0 < 0);
549   -
550 482 /* Branches */
551 483 /* Branch to register */
552 484 void op_save_breg_target (void)
... ...
target-mips/op_helper.c
  View file @3089880
... ... @@ -71,6 +71,16 @@ void do_restore_state (void *pc_ptr)
71 71 }
72 72 }
73 73  
  74 +void do_clo (void)
  75 +{
  76 + T0 = clo32(T0);
  77 +}
  78 +
  79 +void do_clz (void)
  80 +{
  81 + T0 = clz32(T0);
  82 +}
  83 +
74 84 #if defined(TARGET_MIPS64)
75 85 #if TARGET_LONG_BITS > HOST_LONG_BITS
76 86 /* Those might call libgcc functions. */
... ...
target-mips/translate.c
  View file @3089880
... ... @@ -655,6 +655,65 @@ FOP_CONDS(abs, s)
655 655 FOP_CONDS(, ps)
656 656 FOP_CONDS(abs, ps)
657 657  
  658 +/* Tests */
  659 +#define OP_COND(name, cond) \
  660 +void glue(gen_op_, name) (void) \
  661 +{ \
  662 + int l1 = gen_new_label(); \
  663 + int l2 = gen_new_label(); \
  664 + \
  665 + tcg_gen_brcond_tl(cond, cpu_T[0], cpu_T[1], l1); \
  666 + gen_op_set_T0(0); \
  667 + tcg_gen_br(l2); \
  668 + gen_set_label(l1); \
  669 + gen_op_set_T0(1); \
  670 + gen_set_label(l2); \
  671 +}
  672 +OP_COND(eq, TCG_COND_EQ);
  673 +OP_COND(ne, TCG_COND_NE);
  674 +OP_COND(ge, TCG_COND_GE);
  675 +OP_COND(geu, TCG_COND_GEU);
  676 +OP_COND(lt, TCG_COND_LT);
  677 +OP_COND(ltu, TCG_COND_LTU);
  678 +#undef OP_COND
  679 +
  680 +#define OP_CONDI(name, cond) \
  681 +void glue(gen_op_, name) (target_ulong val) \
  682 +{ \
  683 + int l1 = gen_new_label(); \
  684 + int l2 = gen_new_label(); \
  685 + \
  686 + tcg_gen_brcond_tl(cond, cpu_T[0], tcg_const_tl(val), l1); \
  687 + gen_op_set_T0(0); \
  688 + tcg_gen_br(l2); \
  689 + gen_set_label(l1); \
  690 + gen_op_set_T0(1); \
  691 + gen_set_label(l2); \
  692 +}
  693 +OP_CONDI(lti, TCG_COND_LT);
  694 +OP_CONDI(ltiu, TCG_COND_LTU);
  695 +#undef OP_CONDI
  696 +
  697 +#define OP_CONDZ(name, cond) \
  698 +void glue(gen_op_, name) (void) \
  699 +{ \
  700 + int l1 = gen_new_label(); \
  701 + int l2 = gen_new_label(); \
  702 + \
  703 + tcg_gen_brcond_tl(cond, cpu_T[0], tcg_const_tl(0), l1); \
  704 + gen_op_set_T0(0); \
  705 + tcg_gen_br(l2); \
  706 + gen_set_label(l1); \
  707 + gen_op_set_T0(1); \
  708 + gen_set_label(l2); \
  709 +}
  710 +OP_CONDZ(gez, TCG_COND_GE);
  711 +OP_CONDZ(gtz, TCG_COND_GT);
  712 +OP_CONDZ(lez, TCG_COND_LE);
  713 +OP_CONDZ(ltz, TCG_COND_LT);
  714 +#undef OP_CONDZ
  715 +
  716 +
658 717 typedef struct DisasContext {
659 718 struct TranslationBlock *tb;
660 719 target_ulong pc, saved_pc;
... ... @@ -1375,11 +1434,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1375 1434 break;
1376 1435 #endif
1377 1436 case OPC_SLTI:
1378   - gen_op_lt();
  1437 + gen_op_lti(uimm);
1379 1438 opn = "slti";
1380 1439 break;
1381 1440 case OPC_SLTIU:
1382   - gen_op_ltu();
  1441 + gen_op_ltiu(uimm);
1383 1442 opn = "sltiu";
1384 1443 break;
1385 1444 case OPC_ANDI:
... ... @@ -2160,20 +2219,20 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
2160 2219 GEN_LOAD_REG_T0(rs);
2161 2220 switch (opc) {
2162 2221 case OPC_CLO:
2163   - gen_op_clo();
  2222 + tcg_gen_helper_0_0(do_clo);
2164 2223 opn = "clo";
2165 2224 break;
2166 2225 case OPC_CLZ:
2167   - gen_op_clz();
  2226 + tcg_gen_helper_0_0(do_clz);
2168 2227 opn = "clz";
2169 2228 break;
2170 2229 #if defined(TARGET_MIPS64)
2171 2230 case OPC_DCLO:
2172   - gen_op_dclo();
  2231 + tcg_gen_helper_0_0(do_dclo);
2173 2232 opn = "dclo";
2174 2233 break;
2175 2234 case OPC_DCLZ:
2176   - gen_op_dclz();
  2235 + tcg_gen_helper_0_0(do_dclz);
2177 2236 opn = "dclz";
2178 2237 break;
2179 2238 #endif
... ...