gwj / at91sam9263 · Commits

Commit 2f87c60799042f6c9936040cedf6ea8dc690ca22

Authored by bellard
1 parent 03bfca94

Alpha update (Falk Hueffner) 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@203 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 37 additions and 7 deletions
dyngen.c
  View file @2f87c60
... ... @@ -691,7 +691,7 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
691 691 case R_ALPHA_BRSGP:
692 692 /* PC-relative jump. Tweak offset to skip the two instructions that try to
693 693 set up the gp from the pv. */
694   - fprintf(outfile, " fix_bsr(gen_code_ptr + %ld, (uint8_t *) &%s - (gen_code_ptr + %ld) + 4);\n",
  694 + fprintf(outfile, " fix_bsr(gen_code_ptr + %ld, (uint8_t *) &%s - (gen_code_ptr + %ld + 4) + 8);\n",
695 695 rel->r_offset - start_offset, sym_name, rel->r_offset - start_offset);
696 696 break;
697 697 default:
... ...
exec-i386.c
  View file @2f87c60
... ... @@ -447,6 +447,34 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
447 447 is_write, &uc->uc_sigmask);
448 448 }
449 449  
  450 +#elif defined(__alpha__)
  451 +
  452 +int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
  453 + void *puc)
  454 +{
  455 + struct ucontext *uc = puc;
  456 + uint32_t *pc = uc->uc_mcontext.sc_pc;
  457 + uint32_t insn = *pc;
  458 + int is_write = 0;
  459 +
  460 + switch (insn >> 26) {
  461 + case 0x0d: // stw
  462 + case 0x0e: // stb
  463 + case 0x0f: // stq_u
  464 + case 0x24: // stf
  465 + case 0x25: // stg
  466 + case 0x26: // sts
  467 + case 0x27: // stt
  468 + case 0x2c: // stl
  469 + case 0x2d: // stq
  470 + case 0x2e: // stl_c
  471 + case 0x2f: // stq_c
  472 + is_write = 1;
  473 + }
  474 +
  475 + return handle_cpu_signal(pc, (unsigned long)info->si_addr,
  476 + is_write, &uc->uc_sigmask);
  477 +}
450 478 #else
451 479  
452 480 #error CPU specific signal handler needed
... ...
exec-i386.h
  View file @2f87c60
... ... @@ -124,6 +124,8 @@ register unsigned int A0 asm("$11");
124 124 register unsigned int EAX asm("$12");
125 125 register unsigned int ESP asm("$13");
126 126 register unsigned int EBP asm("$14");
  127 +/* Note $15 is the frame pointer, so anything in op-i386.c that would
  128 + require a frame pointer, like alloca, would probably loose. */
127 129 register struct CPUX86State *env asm("$15");
128 130 #define reg_EAX
129 131 #define reg_ESP
... ...
... ... @@ -214,7 +214,7 @@ static inline int testandset (int *p)
214 214 #endif
215 215  
216 216 #ifdef __alpha__
217   -int testandset (int *p)
  217 +static inline int testandset (int *p)
218 218 {
219 219 int ret;
220 220 unsigned long one;
... ...
op-i386.c
  View file @2f87c60
... ... @@ -1762,16 +1762,16 @@ typedef union {
1762 1762 double d;
1763 1763 #ifndef WORDS_BIGENDIAN
1764 1764 struct {
1765   - unsigned long lower;
1766   - long upper;
  1765 + uint32_t lower;
  1766 + int32_t upper;
1767 1767 } l;
1768 1768 #else
1769 1769 struct {
1770   - long upper;
1771   - unsigned long lower;
  1770 + int32_t upper;
  1771 + uint32_t lower;
1772 1772 } l;
1773 1773 #endif
1774   - long long ll;
  1774 + int64_t ll;
1775 1775 } CPU86_LDoubleU;
1776 1776  
1777 1777 /* the following deal with IEEE double-precision numbers */
... ...