gwj / at91sam9263 · Commits

Commit 2f5680ee3307b05a7e49ead7d2cff26cf64f9386

Authored by blueswir1
1 parent ccccab03

Remove some legacy definitions 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4108 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 209 additions and 278 deletions
target-sparc/translate.c
  View file @2f5680e
@@ -112,8 +112,6 @@ static int sign_extend(int x, int len) @@ -112,8 +112,6 @@ static int sign_extend(int x, int len)
112 112
113 #define IS_IMM (insn & (1<<13)) 113 #define IS_IMM (insn & (1<<13))
114 114
115 -static void disas_sparc_insn(DisasContext * dc);  
116 -  
117 /* floating point registers moves */ 115 /* floating point registers moves */
118 static void gen_op_load_fpr_FT0(unsigned int src) 116 static void gen_op_load_fpr_FT0(unsigned int src)
119 { 117 {
@@ -236,11 +234,6 @@ OP_LD_TABLE(lddf); @@ -236,11 +234,6 @@ OP_LD_TABLE(lddf);
236 #define ABI32_MASK(addr) 234 #define ABI32_MASK(addr)
237 #endif 235 #endif
238 236
239 -static inline void gen_movl_simm_T1(int32_t val)  
240 -{  
241 - tcg_gen_movi_tl(cpu_T[1], val);  
242 -}  
243 -  
244 static inline void gen_movl_reg_TN(int reg, TCGv tn) 237 static inline void gen_movl_reg_TN(int reg, TCGv tn)
245 { 238 {
246 if (reg == 0) 239 if (reg == 0)
@@ -252,23 +245,6 @@ static inline void gen_movl_reg_TN(int reg, TCGv tn) @@ -252,23 +245,6 @@ static inline void gen_movl_reg_TN(int reg, TCGv tn)
252 } 245 }
253 } 246 }
254 247
255 -static inline void gen_movl_reg_T0(int reg)  
256 -{  
257 - gen_movl_reg_TN(reg, cpu_T[0]);  
258 -}  
259 -  
260 -static inline void gen_movl_reg_T1(int reg)  
261 -{  
262 - gen_movl_reg_TN(reg, cpu_T[1]);  
263 -}  
264 -  
265 -#ifdef __i386__  
266 -static inline void gen_movl_reg_T2(int reg)  
267 -{  
268 - gen_movl_reg_TN(reg, cpu_T[2]);  
269 -}  
270 -  
271 -#endif /* __i386__ */  
272 static inline void gen_movl_TN_reg(int reg, TCGv tn) 248 static inline void gen_movl_TN_reg(int reg, TCGv tn)
273 { 249 {
274 if (reg == 0) 250 if (reg == 0)
@@ -280,63 +256,6 @@ static inline void gen_movl_TN_reg(int reg, TCGv tn) @@ -280,63 +256,6 @@ static inline void gen_movl_TN_reg(int reg, TCGv tn)
280 } 256 }
281 } 257 }
282 258
283 -static inline void gen_movl_T0_reg(int reg)  
284 -{  
285 - gen_movl_TN_reg(reg, cpu_T[0]);  
286 -}  
287 -  
288 -static inline void gen_movl_T1_reg(int reg)  
289 -{  
290 - gen_movl_TN_reg(reg, cpu_T[1]);  
291 -}  
292 -  
293 -static inline void gen_op_movl_T0_env(size_t offset)  
294 -{  
295 - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offset);  
296 - tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);  
297 -}  
298 -  
299 -static inline void gen_op_movl_env_T0(size_t offset)  
300 -{  
301 - tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);  
302 - tcg_gen_st_i32(cpu_tmp32, cpu_env, offset);  
303 -}  
304 -  
305 -static inline void gen_op_movtl_T0_env(size_t offset)  
306 -{  
307 - tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);  
308 -}  
309 -  
310 -static inline void gen_op_movtl_env_T0(size_t offset)  
311 -{  
312 - tcg_gen_st_tl(cpu_T[0], cpu_env, offset);  
313 -}  
314 -  
315 -static inline void gen_op_add_T1_T0(void)  
316 -{  
317 - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);  
318 -}  
319 -  
320 -static inline void gen_op_or_T1_T0(void)  
321 -{  
322 - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);  
323 -}  
324 -  
325 -static inline void gen_op_xor_T1_T0(void)  
326 -{  
327 - tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);  
328 -}  
329 -  
330 -static inline void gen_jmp_im(target_ulong pc)  
331 -{  
332 - tcg_gen_movi_tl(cpu_pc, pc);  
333 -}  
334 -  
335 -static inline void gen_movl_npc_im(target_ulong npc)  
336 -{  
337 - tcg_gen_movi_tl(cpu_npc, npc);  
338 -}  
339 -  
340 static inline void gen_goto_tb(DisasContext *s, int tb_num, 259 static inline void gen_goto_tb(DisasContext *s, int tb_num,
341 target_ulong pc, target_ulong npc) 260 target_ulong pc, target_ulong npc)
342 { 261 {
@@ -347,13 +266,13 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, @@ -347,13 +266,13 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
347 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { 266 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
348 /* jump to same page: we can use a direct jump */ 267 /* jump to same page: we can use a direct jump */
349 tcg_gen_goto_tb(tb_num); 268 tcg_gen_goto_tb(tb_num);
350 - gen_jmp_im(pc);  
351 - gen_movl_npc_im(npc); 269 + tcg_gen_movi_tl(cpu_pc, pc);
  270 + tcg_gen_movi_tl(cpu_npc, npc);
352 tcg_gen_exit_tb((long)tb + tb_num); 271 tcg_gen_exit_tb((long)tb + tb_num);
353 } else { 272 } else {
354 /* jump to another page: currently not optimized */ 273 /* jump to another page: currently not optimized */
355 - gen_jmp_im(pc);  
356 - gen_movl_npc_im(npc); 274 + tcg_gen_movi_tl(cpu_pc, pc);
  275 + tcg_gen_movi_tl(cpu_npc, npc);
357 tcg_gen_exit_tb(0); 276 tcg_gen_exit_tb(0);
358 } 277 }
359 } 278 }
@@ -387,12 +306,6 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv src) @@ -387,12 +306,6 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv src)
387 tcg_gen_andi_tl(reg, reg, 0x1); 306 tcg_gen_andi_tl(reg, reg, 0x1);
388 } 307 }
389 308
390 -static inline void gen_op_exception(int exception)  
391 -{  
392 - tcg_gen_movi_i32(cpu_tmp32, exception);  
393 - tcg_gen_helper_0_1(raise_exception, cpu_tmp32);  
394 -}  
395 -  
396 static inline void gen_cc_clear(void) 309 static inline void gen_cc_clear(void)
397 { 310 {
398 tcg_gen_movi_i32(cpu_psr, 0); 311 tcg_gen_movi_i32(cpu_psr, 0);
@@ -518,7 +431,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) @@ -518,7 +431,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
518 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); 431 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
519 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); 432 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
520 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); 433 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
521 - gen_op_exception(TT_TOVF); 434 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
522 gen_set_label(l1); 435 gen_set_label(l1);
523 #ifdef TARGET_SPARC64 436 #ifdef TARGET_SPARC64
524 { 437 {
@@ -531,7 +444,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) @@ -531,7 +444,7 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
531 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); 444 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
532 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); 445 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
533 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); 446 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
534 - gen_op_exception(TT_TOVF); 447 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
535 gen_set_label(l2); 448 gen_set_label(l2);
536 } 449 }
537 #endif 450 #endif
@@ -558,7 +471,7 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2) @@ -558,7 +471,7 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2)
558 tcg_gen_or_tl(cpu_tmp0, src1, src2); 471 tcg_gen_or_tl(cpu_tmp0, src1, src2);
559 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); 472 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
560 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); 473 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
561 - gen_op_exception(TT_TOVF); 474 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
562 gen_set_label(l1); 475 gen_set_label(l1);
563 } 476 }
564 477
@@ -685,7 +598,7 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) @@ -685,7 +598,7 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
685 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); 598 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
686 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); 599 tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
687 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); 600 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
688 - gen_op_exception(TT_TOVF); 601 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
689 gen_set_label(l1); 602 gen_set_label(l1);
690 #ifdef TARGET_SPARC64 603 #ifdef TARGET_SPARC64
691 { 604 {
@@ -697,7 +610,7 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) @@ -697,7 +610,7 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
697 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); 610 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
698 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); 611 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
699 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); 612 tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
700 - gen_op_exception(TT_TOVF); 613 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
701 gen_set_label(l2); 614 gen_set_label(l2);
702 } 615 }
703 #endif 616 #endif
@@ -852,16 +765,6 @@ static inline void gen_op_smul_T1_T0(void) @@ -852,16 +765,6 @@ static inline void gen_op_smul_T1_T0(void)
852 tcg_gen_discard_i64(r_temp2); 765 tcg_gen_discard_i64(r_temp2);
853 } 766 }
854 767
855 -static inline void gen_op_udiv_T1_T0(void)  
856 -{  
857 - tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);  
858 -}  
859 -  
860 -static inline void gen_op_sdiv_T1_T0(void)  
861 -{  
862 - tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);  
863 -}  
864 -  
865 #ifdef TARGET_SPARC64 768 #ifdef TARGET_SPARC64
866 static inline void gen_trap_ifdivzero_tl(TCGv divisor) 769 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
867 { 770 {
@@ -869,7 +772,7 @@ static inline void gen_trap_ifdivzero_tl(TCGv divisor) @@ -869,7 +772,7 @@ static inline void gen_trap_ifdivzero_tl(TCGv divisor)
869 772
870 l1 = gen_new_label(); 773 l1 = gen_new_label();
871 tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1); 774 tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
872 - gen_op_exception(TT_DIV_ZERO); 775 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
873 gen_set_label(l1); 776 gen_set_label(l1);
874 } 777 }
875 778
@@ -1210,12 +1113,6 @@ static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, @@ -1210,12 +1113,6 @@ static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1210 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); 1113 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1211 } 1114 }
1212 1115
1213 -static inline void gen_branch(DisasContext *dc, target_ulong pc,  
1214 - target_ulong npc)  
1215 -{  
1216 - gen_goto_tb(dc, 0, pc, npc);  
1217 -}  
1218 -  
1219 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, 1116 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1220 TCGv r_cond) 1117 TCGv r_cond)
1221 { 1118 {
@@ -1226,11 +1123,11 @@ static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, @@ -1226,11 +1123,11 @@ static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1226 1123
1227 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1); 1124 tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1228 1125
1229 - gen_movl_npc_im(npc1); 1126 + tcg_gen_movi_tl(cpu_npc, npc1);
1230 tcg_gen_br(l2); 1127 tcg_gen_br(l2);
1231 1128
1232 gen_set_label(l1); 1129 gen_set_label(l1);
1233 - gen_movl_npc_im(npc2); 1130 + tcg_gen_movi_tl(cpu_npc, npc2);
1234 gen_set_label(l2); 1131 gen_set_label(l2);
1235 } 1132 }
1236 1133
@@ -1249,13 +1146,13 @@ static inline void save_npc(DisasContext * dc) @@ -1249,13 +1146,13 @@ static inline void save_npc(DisasContext * dc)
1249 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); 1146 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
1250 dc->npc = DYNAMIC_PC; 1147 dc->npc = DYNAMIC_PC;
1251 } else if (dc->npc != DYNAMIC_PC) { 1148 } else if (dc->npc != DYNAMIC_PC) {
1252 - gen_movl_npc_im(dc->npc); 1149 + tcg_gen_movi_tl(cpu_npc, dc->npc);
1253 } 1150 }
1254 } 1151 }
1255 1152
1256 static inline void save_state(DisasContext * dc) 1153 static inline void save_state(DisasContext * dc)
1257 { 1154 {
1258 - gen_jmp_im(dc->pc); 1155 + tcg_gen_movi_tl(cpu_pc, dc->pc);
1259 save_npc(dc); 1156 save_npc(dc);
1260 } 1157 }
1261 1158
@@ -1660,7 +1557,7 @@ static inline void gen_op_fpexception_im(int fsr_flags) @@ -1660,7 +1557,7 @@ static inline void gen_op_fpexception_im(int fsr_flags)
1660 { 1557 {
1661 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); 1558 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1662 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); 1559 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1663 - gen_op_exception(TT_FP_EXCP); 1560 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1664 } 1561 }
1665 1562
1666 static int gen_trap_ifnofpu(DisasContext * dc) 1563 static int gen_trap_ifnofpu(DisasContext * dc)
@@ -1668,7 +1565,7 @@ static int gen_trap_ifnofpu(DisasContext * dc) @@ -1668,7 +1565,7 @@ static int gen_trap_ifnofpu(DisasContext * dc)
1668 #if !defined(CONFIG_USER_ONLY) 1565 #if !defined(CONFIG_USER_ONLY)
1669 if (!dc->fpu_enabled) { 1566 if (!dc->fpu_enabled) {
1670 save_state(dc); 1567 save_state(dc);
1671 - gen_op_exception(TT_NFPU_INSN); 1568 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1672 dc->is_br = 1; 1569 dc->is_br = 1;
1673 return 1; 1570 return 1;
1674 } 1571 }
@@ -1947,7 +1844,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1947,7 +1844,7 @@ static void disas_sparc_insn(DisasContext * dc)
1947 target = sign_extend(target, 16); 1844 target = sign_extend(target, 16);
1948 target <<= 2; 1845 target <<= 2;
1949 rs1 = GET_FIELD(insn, 13, 17); 1846 rs1 = GET_FIELD(insn, 13, 17);
1950 - gen_movl_reg_T0(rs1); 1847 + gen_movl_reg_TN(rs1, cpu_T[0]);
1951 do_branch_reg(dc, target, insn); 1848 do_branch_reg(dc, target, insn);
1952 goto jmp_insn; 1849 goto jmp_insn;
1953 } 1850 }
@@ -1993,7 +1890,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1993,7 +1890,7 @@ static void disas_sparc_insn(DisasContext * dc)
1993 #endif 1890 #endif
1994 uint32_t value = GET_FIELD(insn, 10, 31); 1891 uint32_t value = GET_FIELD(insn, 10, 31);
1995 tcg_gen_movi_tl(cpu_T[0], value << 10); 1892 tcg_gen_movi_tl(cpu_T[0], value << 10);
1996 - gen_movl_T0_reg(rd); 1893 + gen_movl_TN_reg(rd, cpu_T[0]);
1997 #if defined(OPTIM) 1894 #if defined(OPTIM)
1998 } 1895 }
1999 #endif 1896 #endif
@@ -2022,7 +1919,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2022,7 +1919,7 @@ static void disas_sparc_insn(DisasContext * dc)
2022 int cond; 1919 int cond;
2023 1920
2024 rs1 = GET_FIELD(insn, 13, 17); 1921 rs1 = GET_FIELD(insn, 13, 17);
2025 - gen_movl_reg_T0(rs1); 1922 + gen_movl_reg_TN(rs1, cpu_T[0]);
2026 if (IS_IMM) { 1923 if (IS_IMM) {
2027 rs2 = GET_FIELD(insn, 25, 31); 1924 rs2 = GET_FIELD(insn, 25, 31);
2028 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2); 1925 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
@@ -2031,8 +1928,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2031,8 +1928,8 @@ static void disas_sparc_insn(DisasContext * dc)
2031 #if defined(OPTIM) 1928 #if defined(OPTIM)
2032 if (rs2 != 0) { 1929 if (rs2 != 0) {
2033 #endif 1930 #endif
2034 - gen_movl_reg_T1(rs2);  
2035 - gen_op_add_T1_T0(); 1931 + gen_movl_reg_TN(rs2, cpu_T[1]);
  1932 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2036 #if defined(OPTIM) 1933 #if defined(OPTIM)
2037 } 1934 }
2038 #endif 1935 #endif
@@ -2079,17 +1976,18 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2079,17 +1976,18 @@ static void disas_sparc_insn(DisasContext * dc)
2079 SPARCv8 manual, rdy on the 1976 SPARCv8 manual, rdy on the
2080 microSPARC II */ 1977 microSPARC II */
2081 #endif 1978 #endif
2082 - gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));  
2083 - gen_movl_T0_reg(rd); 1979 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, y));
  1980 + gen_movl_TN_reg(rd, cpu_T[0]);
2084 break; 1981 break;
2085 #ifdef TARGET_SPARC64 1982 #ifdef TARGET_SPARC64
2086 case 0x2: /* V9 rdccr */ 1983 case 0x2: /* V9 rdccr */
2087 tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]); 1984 tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]);
2088 - gen_movl_T0_reg(rd); 1985 + gen_movl_TN_reg(rd, cpu_T[0]);
2089 break; 1986 break;
2090 case 0x3: /* V9 rdasi */ 1987 case 0x3: /* V9 rdasi */
2091 - gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));  
2092 - gen_movl_T0_reg(rd); 1988 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
  1989 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
  1990 + gen_movl_TN_reg(rd, cpu_T[0]);
2093 break; 1991 break;
2094 case 0x4: /* V9 rdtick */ 1992 case 0x4: /* V9 rdtick */
2095 { 1993 {
@@ -2100,29 +1998,30 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2100,29 +1998,30 @@ static void disas_sparc_insn(DisasContext * dc)
2100 offsetof(CPUState, tick)); 1998 offsetof(CPUState, tick));
2101 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], 1999 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2102 r_tickptr); 2000 r_tickptr);
2103 - gen_movl_T0_reg(rd); 2001 + gen_movl_TN_reg(rd, cpu_T[0]);
2104 tcg_gen_discard_ptr(r_tickptr); 2002 tcg_gen_discard_ptr(r_tickptr);
2105 } 2003 }
2106 break; 2004 break;
2107 case 0x5: /* V9 rdpc */ 2005 case 0x5: /* V9 rdpc */
2108 tcg_gen_movi_tl(cpu_T[0], dc->pc); 2006 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2109 - gen_movl_T0_reg(rd); 2007 + gen_movl_TN_reg(rd, cpu_T[0]);
2110 break; 2008 break;
2111 case 0x6: /* V9 rdfprs */ 2009 case 0x6: /* V9 rdfprs */
2112 - gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));  
2113 - gen_movl_T0_reg(rd); 2010 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
  2011 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
  2012 + gen_movl_TN_reg(rd, cpu_T[0]);
2114 break; 2013 break;
2115 case 0xf: /* V9 membar */ 2014 case 0xf: /* V9 membar */
2116 break; /* no effect */ 2015 break; /* no effect */
2117 case 0x13: /* Graphics Status */ 2016 case 0x13: /* Graphics Status */
2118 if (gen_trap_ifnofpu(dc)) 2017 if (gen_trap_ifnofpu(dc))
2119 goto jmp_insn; 2018 goto jmp_insn;
2120 - gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));  
2121 - gen_movl_T0_reg(rd); 2019 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
  2020 + gen_movl_TN_reg(rd, cpu_T[0]);
2122 break; 2021 break;
2123 case 0x17: /* Tick compare */ 2022 case 0x17: /* Tick compare */
2124 - gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));  
2125 - gen_movl_T0_reg(rd); 2023 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tick_cmpr));
  2024 + gen_movl_TN_reg(rd, cpu_T[0]);
2126 break; 2025 break;
2127 case 0x18: /* System tick */ 2026 case 0x18: /* System tick */
2128 { 2027 {
@@ -2133,13 +2032,13 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2133,13 +2032,13 @@ static void disas_sparc_insn(DisasContext * dc)
2133 offsetof(CPUState, stick)); 2032 offsetof(CPUState, stick));
2134 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], 2033 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2135 r_tickptr); 2034 r_tickptr);
2136 - gen_movl_T0_reg(rd); 2035 + gen_movl_TN_reg(rd, cpu_T[0]);
2137 tcg_gen_discard_ptr(r_tickptr); 2036 tcg_gen_discard_ptr(r_tickptr);
2138 } 2037 }
2139 break; 2038 break;
2140 case 0x19: /* System tick compare */ 2039 case 0x19: /* System tick compare */
2141 - gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));  
2142 - gen_movl_T0_reg(rd); 2040 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, stick_cmpr));
  2041 + gen_movl_TN_reg(rd, cpu_T[0]);
2143 break; 2042 break;
2144 case 0x10: /* Performance Control */ 2043 case 0x10: /* Performance Control */
2145 case 0x11: /* Performance Instrumentation Counter */ 2044 case 0x11: /* Performance Instrumentation Counter */
@@ -2169,22 +2068,26 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2169,22 +2068,26 @@ static void disas_sparc_insn(DisasContext * dc)
2169 // gen_op_rdhtstate(); 2068 // gen_op_rdhtstate();
2170 break; 2069 break;
2171 case 3: // hintp 2070 case 3: // hintp
2172 - gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); 2071 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
  2072 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2173 break; 2073 break;
2174 case 5: // htba 2074 case 5: // htba
2175 - gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); 2075 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
  2076 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2176 break; 2077 break;
2177 case 6: // hver 2078 case 6: // hver
2178 - gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); 2079 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
  2080 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2179 break; 2081 break;
2180 case 31: // hstick_cmpr 2082 case 31: // hstick_cmpr
2181 - gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); 2083 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  2084 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
2182 break; 2085 break;
2183 default: 2086 default:
2184 goto illegal_insn; 2087 goto illegal_insn;
2185 } 2088 }
2186 #endif 2089 #endif
2187 - gen_movl_T0_reg(rd); 2090 + gen_movl_TN_reg(rd, cpu_T[0]);
2188 break; 2091 break;
2189 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ 2092 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2190 if (!supervisor(dc)) 2093 if (!supervisor(dc))
@@ -2249,59 +2152,70 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2249,59 +2152,70 @@ static void disas_sparc_insn(DisasContext * dc)
2249 offsetof(CPUState, tick)); 2152 offsetof(CPUState, tick));
2250 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], 2153 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
2251 r_tickptr); 2154 r_tickptr);
2252 - gen_movl_T0_reg(rd); 2155 + gen_movl_TN_reg(rd, cpu_T[0]);
2253 tcg_gen_discard_ptr(r_tickptr); 2156 tcg_gen_discard_ptr(r_tickptr);
2254 } 2157 }
2255 break; 2158 break;
2256 case 5: // tba 2159 case 5: // tba
2257 - gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); 2160 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
2258 break; 2161 break;
2259 case 6: // pstate 2162 case 6: // pstate
2260 - gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate)); 2163 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
  2164 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2261 break; 2165 break;
2262 case 7: // tl 2166 case 7: // tl
2263 - gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); 2167 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
  2168 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2264 break; 2169 break;
2265 case 8: // pil 2170 case 8: // pil
2266 - gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); 2171 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
  2172 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2267 break; 2173 break;
2268 case 9: // cwp 2174 case 9: // cwp
2269 tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]); 2175 tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]);
2270 break; 2176 break;
2271 case 10: // cansave 2177 case 10: // cansave
2272 - gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); 2178 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
  2179 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2273 break; 2180 break;
2274 case 11: // canrestore 2181 case 11: // canrestore
2275 - gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); 2182 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
  2183 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2276 break; 2184 break;
2277 case 12: // cleanwin 2185 case 12: // cleanwin
2278 - gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); 2186 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
  2187 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2279 break; 2188 break;
2280 case 13: // otherwin 2189 case 13: // otherwin
2281 - gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); 2190 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
  2191 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2282 break; 2192 break;
2283 case 14: // wstate 2193 case 14: // wstate
2284 - gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); 2194 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
  2195 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2285 break; 2196 break;
2286 case 16: // UA2005 gl 2197 case 16: // UA2005 gl
2287 - gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); 2198 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
  2199 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2288 break; 2200 break;
2289 case 26: // UA2005 strand status 2201 case 26: // UA2005 strand status
2290 if (!hypervisor(dc)) 2202 if (!hypervisor(dc))
2291 goto priv_insn; 2203 goto priv_insn;
2292 - gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); 2204 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
  2205 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2293 break; 2206 break;
2294 case 31: // ver 2207 case 31: // ver
2295 - gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); 2208 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, version));
2296 break; 2209 break;
2297 case 15: // fq 2210 case 15: // fq
2298 default: 2211 default:
2299 goto illegal_insn; 2212 goto illegal_insn;
2300 } 2213 }
2301 #else 2214 #else
2302 - gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); 2215 + tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
  2216 + tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
2303 #endif 2217 #endif
2304 - gen_movl_T0_reg(rd); 2218 + gen_movl_TN_reg(rd, cpu_T[0]);
2305 break; 2219 break;
2306 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ 2220 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2307 #ifdef TARGET_SPARC64 2221 #ifdef TARGET_SPARC64
@@ -2309,8 +2223,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2309,8 +2223,8 @@ static void disas_sparc_insn(DisasContext * dc)
2309 #else 2223 #else
2310 if (!supervisor(dc)) 2224 if (!supervisor(dc))
2311 goto priv_insn; 2225 goto priv_insn;
2312 - gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));  
2313 - gen_movl_T0_reg(rd); 2226 + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
  2227 + gen_movl_TN_reg(rd, cpu_T[0]);
2314 #endif 2228 #endif
2315 break; 2229 break;
2316 #endif 2230 #endif
@@ -2703,7 +2617,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2703,7 +2617,7 @@ static void disas_sparc_insn(DisasContext * dc)
2703 l1 = gen_new_label(); 2617 l1 = gen_new_label();
2704 cond = GET_FIELD_SP(insn, 14, 17); 2618 cond = GET_FIELD_SP(insn, 14, 17);
2705 rs1 = GET_FIELD(insn, 13, 17); 2619 rs1 = GET_FIELD(insn, 13, 17);
2706 - gen_movl_reg_T0(rs1); 2620 + gen_movl_reg_TN(rs1, cpu_T[0]);
2707 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], 2621 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2708 tcg_const_tl(0), l1); 2622 tcg_const_tl(0), l1);
2709 gen_op_load_fpr_FT0(rs2); 2623 gen_op_load_fpr_FT0(rs2);
@@ -2716,7 +2630,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2716,7 +2630,7 @@ static void disas_sparc_insn(DisasContext * dc)
2716 l1 = gen_new_label(); 2630 l1 = gen_new_label();
2717 cond = GET_FIELD_SP(insn, 14, 17); 2631 cond = GET_FIELD_SP(insn, 14, 17);
2718 rs1 = GET_FIELD(insn, 13, 17); 2632 rs1 = GET_FIELD(insn, 13, 17);
2719 - gen_movl_reg_T0(rs1); 2633 + gen_movl_reg_TN(rs1, cpu_T[0]);
2720 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], 2634 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2721 tcg_const_tl(0), l1); 2635 tcg_const_tl(0), l1);
2722 gen_op_load_fpr_DT0(DFPREG(rs2)); 2636 gen_op_load_fpr_DT0(DFPREG(rs2));
@@ -2730,7 +2644,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2730,7 +2644,7 @@ static void disas_sparc_insn(DisasContext * dc)
2730 l1 = gen_new_label(); 2644 l1 = gen_new_label();
2731 cond = GET_FIELD_SP(insn, 14, 17); 2645 cond = GET_FIELD_SP(insn, 14, 17);
2732 rs1 = GET_FIELD(insn, 13, 17); 2646 rs1 = GET_FIELD(insn, 13, 17);
2733 - gen_movl_reg_T0(rs1); 2647 + gen_movl_reg_TN(rs1, cpu_T[0]);
2734 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], 2648 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
2735 tcg_const_tl(0), l1); 2649 tcg_const_tl(0), l1);
2736 gen_op_load_fpr_QT0(QFPREG(rs2)); 2650 gen_op_load_fpr_QT0(QFPREG(rs2));
@@ -2910,10 +2824,10 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2910,10 +2824,10 @@ static void disas_sparc_insn(DisasContext * dc)
2910 tcg_gen_movi_tl(cpu_T[0], (int)rs2); 2824 tcg_gen_movi_tl(cpu_T[0], (int)rs2);
2911 } else { /* register */ 2825 } else { /* register */
2912 rs2 = GET_FIELD(insn, 27, 31); 2826 rs2 = GET_FIELD(insn, 27, 31);
2913 - gen_movl_reg_T0(rs2); 2827 + gen_movl_reg_TN(rs2, cpu_T[0]);
2914 } 2828 }
2915 } else { 2829 } else {
2916 - gen_movl_reg_T0(rs1); 2830 + gen_movl_reg_TN(rs1, cpu_T[0]);
2917 if (IS_IMM) { /* immediate */ 2831 if (IS_IMM) { /* immediate */
2918 rs2 = GET_FIELDs(insn, 19, 31); 2832 rs2 = GET_FIELDs(insn, 19, 31);
2919 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2); 2833 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
@@ -2921,17 +2835,17 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2921,17 +2835,17 @@ static void disas_sparc_insn(DisasContext * dc)
2921 // or x, %g0, y -> mov T1, x; mov y, T1 2835 // or x, %g0, y -> mov T1, x; mov y, T1
2922 rs2 = GET_FIELD(insn, 27, 31); 2836 rs2 = GET_FIELD(insn, 27, 31);
2923 if (rs2 != 0) { 2837 if (rs2 != 0) {
2924 - gen_movl_reg_T1(rs2);  
2925 - gen_op_or_T1_T0(); 2838 + gen_movl_reg_TN(rs2, cpu_T[1]);
  2839 + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2926 } 2840 }
2927 } 2841 }
2928 } 2842 }
2929 - gen_movl_T0_reg(rd); 2843 + gen_movl_TN_reg(rd, cpu_T[0]);
2930 #endif 2844 #endif
2931 #ifdef TARGET_SPARC64 2845 #ifdef TARGET_SPARC64
2932 } else if (xop == 0x25) { /* sll, V9 sllx */ 2846 } else if (xop == 0x25) { /* sll, V9 sllx */
2933 rs1 = GET_FIELD(insn, 13, 17); 2847 rs1 = GET_FIELD(insn, 13, 17);
2934 - gen_movl_reg_T0(rs1); 2848 + gen_movl_reg_TN(rs1, cpu_T[0]);
2935 if (IS_IMM) { /* immediate */ 2849 if (IS_IMM) { /* immediate */
2936 rs2 = GET_FIELDs(insn, 20, 31); 2850 rs2 = GET_FIELDs(insn, 20, 31);
2937 if (insn & (1 << 12)) { 2851 if (insn & (1 << 12)) {
@@ -2942,7 +2856,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2942,7 +2856,7 @@ static void disas_sparc_insn(DisasContext * dc)
2942 } 2856 }
2943 } else { /* register */ 2857 } else { /* register */
2944 rs2 = GET_FIELD(insn, 27, 31); 2858 rs2 = GET_FIELD(insn, 27, 31);
2945 - gen_movl_reg_T1(rs2); 2859 + gen_movl_reg_TN(rs2, cpu_T[1]);
2946 if (insn & (1 << 12)) { 2860 if (insn & (1 << 12)) {
2947 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); 2861 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2948 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); 2862 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
@@ -2952,10 +2866,10 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2952,10 +2866,10 @@ static void disas_sparc_insn(DisasContext * dc)
2952 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); 2866 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2953 } 2867 }
2954 } 2868 }
2955 - gen_movl_T0_reg(rd); 2869 + gen_movl_TN_reg(rd, cpu_T[0]);
2956 } else if (xop == 0x26) { /* srl, V9 srlx */ 2870 } else if (xop == 0x26) { /* srl, V9 srlx */
2957 rs1 = GET_FIELD(insn, 13, 17); 2871 rs1 = GET_FIELD(insn, 13, 17);
2958 - gen_movl_reg_T0(rs1); 2872 + gen_movl_reg_TN(rs1, cpu_T[0]);
2959 if (IS_IMM) { /* immediate */ 2873 if (IS_IMM) { /* immediate */
2960 rs2 = GET_FIELDs(insn, 20, 31); 2874 rs2 = GET_FIELDs(insn, 20, 31);
2961 if (insn & (1 << 12)) { 2875 if (insn & (1 << 12)) {
@@ -2966,7 +2880,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2966,7 +2880,7 @@ static void disas_sparc_insn(DisasContext * dc)
2966 } 2880 }
2967 } else { /* register */ 2881 } else { /* register */
2968 rs2 = GET_FIELD(insn, 27, 31); 2882 rs2 = GET_FIELD(insn, 27, 31);
2969 - gen_movl_reg_T1(rs2); 2883 + gen_movl_reg_TN(rs2, cpu_T[1]);
2970 if (insn & (1 << 12)) { 2884 if (insn & (1 << 12)) {
2971 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); 2885 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2972 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); 2886 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
@@ -2976,10 +2890,10 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2976,10 +2890,10 @@ static void disas_sparc_insn(DisasContext * dc)
2976 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); 2890 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2977 } 2891 }
2978 } 2892 }
2979 - gen_movl_T0_reg(rd); 2893 + gen_movl_TN_reg(rd, cpu_T[0]);
2980 } else if (xop == 0x27) { /* sra, V9 srax */ 2894 } else if (xop == 0x27) { /* sra, V9 srax */
2981 rs1 = GET_FIELD(insn, 13, 17); 2895 rs1 = GET_FIELD(insn, 13, 17);
2982 - gen_movl_reg_T0(rs1); 2896 + gen_movl_reg_TN(rs1, cpu_T[0]);
2983 if (IS_IMM) { /* immediate */ 2897 if (IS_IMM) { /* immediate */
2984 rs2 = GET_FIELDs(insn, 20, 31); 2898 rs2 = GET_FIELDs(insn, 20, 31);
2985 if (insn & (1 << 12)) { 2899 if (insn & (1 << 12)) {
@@ -2991,7 +2905,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2991,7 +2905,7 @@ static void disas_sparc_insn(DisasContext * dc)
2991 } 2905 }
2992 } else { /* register */ 2906 } else { /* register */
2993 rs2 = GET_FIELD(insn, 27, 31); 2907 rs2 = GET_FIELD(insn, 27, 31);
2994 - gen_movl_reg_T1(rs2); 2908 + gen_movl_reg_TN(rs2, cpu_T[1]);
2995 if (insn & (1 << 12)) { 2909 if (insn & (1 << 12)) {
2996 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); 2910 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2997 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); 2911 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
@@ -3001,17 +2915,17 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3001,17 +2915,17 @@ static void disas_sparc_insn(DisasContext * dc)
3001 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); 2915 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
3002 } 2916 }
3003 } 2917 }
3004 - gen_movl_T0_reg(rd); 2918 + gen_movl_TN_reg(rd, cpu_T[0]);
3005 #endif 2919 #endif
3006 } else if (xop < 0x36) { 2920 } else if (xop < 0x36) {
3007 rs1 = GET_FIELD(insn, 13, 17); 2921 rs1 = GET_FIELD(insn, 13, 17);
3008 - gen_movl_reg_T0(rs1); 2922 + gen_movl_reg_TN(rs1, cpu_T[0]);
3009 if (IS_IMM) { /* immediate */ 2923 if (IS_IMM) { /* immediate */
3010 rs2 = GET_FIELDs(insn, 19, 31); 2924 rs2 = GET_FIELDs(insn, 19, 31);
3011 - gen_movl_simm_T1(rs2); 2925 + tcg_gen_movi_tl(cpu_T[1], (int)rs2);
3012 } else { /* register */ 2926 } else { /* register */
3013 rs2 = GET_FIELD(insn, 27, 31); 2927 rs2 = GET_FIELD(insn, 27, 31);
3014 - gen_movl_reg_T1(rs2); 2928 + gen_movl_reg_TN(rs2, cpu_T[1]);
3015 } 2929 }
3016 if (xop < 0x20) { 2930 if (xop < 0x20) {
3017 switch (xop & ~0x10) { 2931 switch (xop & ~0x10) {
@@ -3019,7 +2933,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3019,7 +2933,7 @@ static void disas_sparc_insn(DisasContext * dc)
3019 if (xop & 0x10) 2933 if (xop & 0x10)
3020 gen_op_add_T1_T0_cc(); 2934 gen_op_add_T1_T0_cc();
3021 else 2935 else
3022 - gen_op_add_T1_T0(); 2936 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3023 break; 2937 break;
3024 case 0x1: 2938 case 0x1:
3025 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2939 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
@@ -3100,66 +3014,66 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3100,66 +3014,66 @@ static void disas_sparc_insn(DisasContext * dc)
3100 break; 3014 break;
3101 #endif 3015 #endif
3102 case 0xe: 3016 case 0xe:
3103 - gen_op_udiv_T1_T0(); 3017 + tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);
3104 if (xop & 0x10) 3018 if (xop & 0x10)
3105 gen_op_div_cc(); 3019 gen_op_div_cc();
3106 break; 3020 break;
3107 case 0xf: 3021 case 0xf:
3108 - gen_op_sdiv_T1_T0(); 3022 + tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);
3109 if (xop & 0x10) 3023 if (xop & 0x10)
3110 gen_op_div_cc(); 3024 gen_op_div_cc();
3111 break; 3025 break;
3112 default: 3026 default:
3113 goto illegal_insn; 3027 goto illegal_insn;
3114 } 3028 }
3115 - gen_movl_T0_reg(rd); 3029 + gen_movl_TN_reg(rd, cpu_T[0]);
3116 } else { 3030 } else {
3117 switch (xop) { 3031 switch (xop) {
3118 case 0x20: /* taddcc */ 3032 case 0x20: /* taddcc */
3119 gen_op_tadd_T1_T0_cc(); 3033 gen_op_tadd_T1_T0_cc();
3120 - gen_movl_T0_reg(rd); 3034 + gen_movl_TN_reg(rd, cpu_T[0]);
3121 break; 3035 break;
3122 case 0x21: /* tsubcc */ 3036 case 0x21: /* tsubcc */
3123 gen_op_tsub_T1_T0_cc(); 3037 gen_op_tsub_T1_T0_cc();
3124 - gen_movl_T0_reg(rd); 3038 + gen_movl_TN_reg(rd, cpu_T[0]);
3125 break; 3039 break;
3126 case 0x22: /* taddcctv */ 3040 case 0x22: /* taddcctv */
3127 save_state(dc); 3041 save_state(dc);
3128 gen_op_tadd_T1_T0_ccTV(); 3042 gen_op_tadd_T1_T0_ccTV();
3129 - gen_movl_T0_reg(rd); 3043 + gen_movl_TN_reg(rd, cpu_T[0]);
3130 break; 3044 break;
3131 case 0x23: /* tsubcctv */ 3045 case 0x23: /* tsubcctv */
3132 save_state(dc); 3046 save_state(dc);
3133 gen_op_tsub_T1_T0_ccTV(); 3047 gen_op_tsub_T1_T0_ccTV();
3134 - gen_movl_T0_reg(rd); 3048 + gen_movl_TN_reg(rd, cpu_T[0]);
3135 break; 3049 break;
3136 case 0x24: /* mulscc */ 3050 case 0x24: /* mulscc */
3137 gen_op_mulscc_T1_T0(); 3051 gen_op_mulscc_T1_T0();
3138 - gen_movl_T0_reg(rd); 3052 + gen_movl_TN_reg(rd, cpu_T[0]);
3139 break; 3053 break;
3140 #ifndef TARGET_SPARC64 3054 #ifndef TARGET_SPARC64
3141 case 0x25: /* sll */ 3055 case 0x25: /* sll */
3142 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f); 3056 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
3143 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 3057 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3144 - gen_movl_T0_reg(rd); 3058 + gen_movl_TN_reg(rd, cpu_T[0]);
3145 break; 3059 break;
3146 case 0x26: /* srl */ 3060 case 0x26: /* srl */
3147 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f); 3061 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
3148 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 3062 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3149 - gen_movl_T0_reg(rd); 3063 + gen_movl_TN_reg(rd, cpu_T[0]);
3150 break; 3064 break;
3151 case 0x27: /* sra */ 3065 case 0x27: /* sra */
3152 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f); 3066 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f);
3153 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 3067 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3154 - gen_movl_T0_reg(rd); 3068 + gen_movl_TN_reg(rd, cpu_T[0]);
3155 break; 3069 break;
3156 #endif 3070 #endif
3157 case 0x30: 3071 case 0x30:
3158 { 3072 {
3159 switch(rd) { 3073 switch(rd) {
3160 case 0: /* wry */ 3074 case 0: /* wry */
3161 - gen_op_xor_T1_T0();  
3162 - gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); 3075 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  3076 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, y));
3163 break; 3077 break;
3164 #ifndef TARGET_SPARC64 3078 #ifndef TARGET_SPARC64
3165 case 0x01 ... 0x0f: /* undefined in the 3079 case 0x01 ... 0x0f: /* undefined in the
@@ -3173,16 +3087,18 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3173,16 +3087,18 @@ static void disas_sparc_insn(DisasContext * dc)
3173 break; 3087 break;
3174 #else 3088 #else
3175 case 0x2: /* V9 wrccr */ 3089 case 0x2: /* V9 wrccr */
3176 - gen_op_xor_T1_T0(); 3090 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3177 tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]); 3091 tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]);
3178 break; 3092 break;
3179 case 0x3: /* V9 wrasi */ 3093 case 0x3: /* V9 wrasi */
3180 - gen_op_xor_T1_T0();  
3181 - gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); 3094 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  3095 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3096 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
3182 break; 3097 break;
3183 case 0x6: /* V9 wrfprs */ 3098 case 0x6: /* V9 wrfprs */
3184 - gen_op_xor_T1_T0();  
3185 - gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); 3099 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  3100 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3101 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
3186 save_state(dc); 3102 save_state(dc);
3187 gen_op_next_insn(); 3103 gen_op_next_insn();
3188 tcg_gen_exit_tb(0); 3104 tcg_gen_exit_tb(0);
@@ -3197,8 +3113,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3197,8 +3113,8 @@ static void disas_sparc_insn(DisasContext * dc)
3197 case 0x13: /* Graphics Status */ 3113 case 0x13: /* Graphics Status */
3198 if (gen_trap_ifnofpu(dc)) 3114 if (gen_trap_ifnofpu(dc))
3199 goto jmp_insn; 3115 goto jmp_insn;
3200 - gen_op_xor_T1_T0();  
3201 - gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); 3116 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  3117 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
3202 break; 3118 break;
3203 case 0x17: /* Tick compare */ 3119 case 0x17: /* Tick compare */
3204 #if !defined(CONFIG_USER_ONLY) 3120 #if !defined(CONFIG_USER_ONLY)
@@ -3208,8 +3124,9 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3208,8 +3124,9 @@ static void disas_sparc_insn(DisasContext * dc)
3208 { 3124 {
3209 TCGv r_tickptr; 3125 TCGv r_tickptr;
3210 3126
3211 - gen_op_xor_T1_T0();  
3212 - gen_op_movtl_env_T0(offsetof(CPUSPARCState, 3127 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
  3128 + cpu_T[1]);
  3129 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
3213 tick_cmpr)); 3130 tick_cmpr));
3214 r_tickptr = tcg_temp_new(TCG_TYPE_PTR); 3131 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3215 tcg_gen_ld_ptr(r_tickptr, cpu_env, 3132 tcg_gen_ld_ptr(r_tickptr, cpu_env,
@@ -3227,7 +3144,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3227,7 +3144,8 @@ static void disas_sparc_insn(DisasContext * dc)
3227 { 3144 {
3228 TCGv r_tickptr; 3145 TCGv r_tickptr;
3229 3146
3230 - gen_op_xor_T1_T0(); 3147 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
  3148 + cpu_T[1]);
3231 r_tickptr = tcg_temp_new(TCG_TYPE_PTR); 3149 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3232 tcg_gen_ld_ptr(r_tickptr, cpu_env, 3150 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3233 offsetof(CPUState, stick)); 3151 offsetof(CPUState, stick));
@@ -3244,8 +3162,9 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3244,8 +3162,9 @@ static void disas_sparc_insn(DisasContext * dc)
3244 { 3162 {
3245 TCGv r_tickptr; 3163 TCGv r_tickptr;
3246 3164
3247 - gen_op_xor_T1_T0();  
3248 - gen_op_movtl_env_T0(offsetof(CPUSPARCState, 3165 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0],
  3166 + cpu_T[1]);
  3167 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
3249 stick_cmpr)); 3168 stick_cmpr));
3250 r_tickptr = tcg_temp_new(TCG_TYPE_PTR); 3169 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3251 tcg_gen_ld_ptr(r_tickptr, cpu_env, 3170 tcg_gen_ld_ptr(r_tickptr, cpu_env,
@@ -3290,7 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3290,7 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc)
3290 goto illegal_insn; 3209 goto illegal_insn;
3291 } 3210 }
3292 #else 3211 #else
3293 - gen_op_xor_T1_T0(); 3212 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3294 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]); 3213 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
3295 save_state(dc); 3214 save_state(dc);
3296 gen_op_next_insn(); 3215 gen_op_next_insn();
@@ -3303,7 +3222,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3303,7 +3222,7 @@ static void disas_sparc_insn(DisasContext * dc)
3303 { 3222 {
3304 if (!supervisor(dc)) 3223 if (!supervisor(dc))
3305 goto priv_insn; 3224 goto priv_insn;
3306 - gen_op_xor_T1_T0(); 3225 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3307 #ifdef TARGET_SPARC64 3226 #ifdef TARGET_SPARC64
3308 switch (rd) { 3227 switch (rd) {
3309 case 0: // tpc 3228 case 0: // tpc
@@ -3367,7 +3286,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3367,7 +3286,7 @@ static void disas_sparc_insn(DisasContext * dc)
3367 } 3286 }
3368 break; 3287 break;
3369 case 5: // tba 3288 case 5: // tba
3370 - gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); 3289 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
3371 break; 3290 break;
3372 case 6: // pstate 3291 case 6: // pstate
3373 save_state(dc); 3292 save_state(dc);
@@ -3377,43 +3296,53 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3377,43 +3296,53 @@ static void disas_sparc_insn(DisasContext * dc)
3377 dc->is_br = 1; 3296 dc->is_br = 1;
3378 break; 3297 break;
3379 case 7: // tl 3298 case 7: // tl
3380 - gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); 3299 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3300 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
3381 break; 3301 break;
3382 case 8: // pil 3302 case 8: // pil
3383 - gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); 3303 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3304 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
3384 break; 3305 break;
3385 case 9: // cwp 3306 case 9: // cwp
3386 tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]); 3307 tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]);
3387 break; 3308 break;
3388 case 10: // cansave 3309 case 10: // cansave
3389 - gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); 3310 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3311 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
3390 break; 3312 break;
3391 case 11: // canrestore 3313 case 11: // canrestore
3392 - gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); 3314 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3315 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
3393 break; 3316 break;
3394 case 12: // cleanwin 3317 case 12: // cleanwin
3395 - gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); 3318 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3319 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
3396 break; 3320 break;
3397 case 13: // otherwin 3321 case 13: // otherwin
3398 - gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); 3322 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3323 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
3399 break; 3324 break;
3400 case 14: // wstate 3325 case 14: // wstate
3401 - gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); 3326 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3327 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
3402 break; 3328 break;
3403 case 16: // UA2005 gl 3329 case 16: // UA2005 gl
3404 - gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); 3330 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3331 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
3405 break; 3332 break;
3406 case 26: // UA2005 strand status 3333 case 26: // UA2005 strand status
3407 if (!hypervisor(dc)) 3334 if (!hypervisor(dc))
3408 goto priv_insn; 3335 goto priv_insn;
3409 - gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); 3336 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3337 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
3410 break; 3338 break;
3411 default: 3339 default:
3412 goto illegal_insn; 3340 goto illegal_insn;
3413 } 3341 }
3414 #else 3342 #else
3415 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1)); 3343 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
3416 - gen_op_movl_env_T0(offsetof(CPUSPARCState, wim)); 3344 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3345 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
3417 #endif 3346 #endif
3418 } 3347 }
3419 break; 3348 break;
@@ -3422,12 +3351,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3422,12 +3351,12 @@ static void disas_sparc_insn(DisasContext * dc)
3422 #ifndef TARGET_SPARC64 3351 #ifndef TARGET_SPARC64
3423 if (!supervisor(dc)) 3352 if (!supervisor(dc))
3424 goto priv_insn; 3353 goto priv_insn;
3425 - gen_op_xor_T1_T0();  
3426 - gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); 3354 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  3355 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
3427 #else 3356 #else
3428 if (!hypervisor(dc)) 3357 if (!hypervisor(dc))
3429 goto priv_insn; 3358 goto priv_insn;
3430 - gen_op_xor_T1_T0(); 3359 + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3431 switch (rd) { 3360 switch (rd) {
3432 case 0: // hpstate 3361 case 0: // hpstate
3433 // XXX gen_op_wrhpstate(); 3362 // XXX gen_op_wrhpstate();
@@ -3440,16 +3369,18 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3440,16 +3369,18 @@ static void disas_sparc_insn(DisasContext * dc)
3440 // XXX gen_op_wrhtstate(); 3369 // XXX gen_op_wrhtstate();
3441 break; 3370 break;
3442 case 3: // hintp 3371 case 3: // hintp
3443 - gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); 3372 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3373 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
3444 break; 3374 break;
3445 case 5: // htba 3375 case 5: // htba
3446 - gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); 3376 + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
  3377 + tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
3447 break; 3378 break;
3448 case 31: // hstick_cmpr 3379 case 31: // hstick_cmpr
3449 { 3380 {
3450 TCGv r_tickptr; 3381 TCGv r_tickptr;
3451 3382
3452 - gen_op_movtl_env_T0(offsetof(CPUSPARCState, 3383 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState,
3453 hstick_cmpr)); 3384 hstick_cmpr));
3454 r_tickptr = tcg_temp_new(TCG_TYPE_PTR); 3385 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3455 tcg_gen_ld_ptr(r_tickptr, cpu_env, 3386 tcg_gen_ld_ptr(r_tickptr, cpu_env,
@@ -3493,34 +3424,34 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3493,34 +3424,34 @@ static void disas_sparc_insn(DisasContext * dc)
3493 tcg_const_tl(0), l1); 3424 tcg_const_tl(0), l1);
3494 if (IS_IMM) { /* immediate */ 3425 if (IS_IMM) { /* immediate */
3495 rs2 = GET_FIELD_SPs(insn, 0, 10); 3426 rs2 = GET_FIELD_SPs(insn, 0, 10);
3496 - gen_movl_simm_T1(rs2); 3427 + tcg_gen_movi_tl(cpu_T[1], (int)rs2);
3497 } else { 3428 } else {
3498 rs2 = GET_FIELD_SP(insn, 0, 4); 3429 rs2 = GET_FIELD_SP(insn, 0, 4);
3499 - gen_movl_reg_T1(rs2); 3430 + gen_movl_reg_TN(rs2, cpu_T[1]);
3500 } 3431 }
3501 - gen_movl_T1_reg(rd); 3432 + gen_movl_TN_reg(rd, cpu_T[1]);
3502 gen_set_label(l1); 3433 gen_set_label(l1);
3503 tcg_gen_discard_tl(r_cond); 3434 tcg_gen_discard_tl(r_cond);
3504 break; 3435 break;
3505 } 3436 }
3506 case 0x2d: /* V9 sdivx */ 3437 case 0x2d: /* V9 sdivx */
3507 gen_op_sdivx_T1_T0(); 3438 gen_op_sdivx_T1_T0();
3508 - gen_movl_T0_reg(rd); 3439 + gen_movl_TN_reg(rd, cpu_T[0]);
3509 break; 3440 break;
3510 case 0x2e: /* V9 popc */ 3441 case 0x2e: /* V9 popc */
3511 { 3442 {
3512 if (IS_IMM) { /* immediate */ 3443 if (IS_IMM) { /* immediate */
3513 rs2 = GET_FIELD_SPs(insn, 0, 12); 3444 rs2 = GET_FIELD_SPs(insn, 0, 12);
3514 - gen_movl_simm_T1(rs2); 3445 + tcg_gen_movi_tl(cpu_T[1], (int)rs2);
3515 // XXX optimize: popc(constant) 3446 // XXX optimize: popc(constant)
3516 } 3447 }
3517 else { 3448 else {
3518 rs2 = GET_FIELD_SP(insn, 0, 4); 3449 rs2 = GET_FIELD_SP(insn, 0, 4);
3519 - gen_movl_reg_T1(rs2); 3450 + gen_movl_reg_TN(rs2, cpu_T[1]);
3520 } 3451 }
3521 tcg_gen_helper_1_1(helper_popc, cpu_T[0], 3452 tcg_gen_helper_1_1(helper_popc, cpu_T[0],
3522 cpu_T[1]); 3453 cpu_T[1]);
3523 - gen_movl_T0_reg(rd); 3454 + gen_movl_TN_reg(rd, cpu_T[0]);
3524 } 3455 }
3525 case 0x2f: /* V9 movr */ 3456 case 0x2f: /* V9 movr */
3526 { 3457 {
@@ -3528,7 +3459,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3528,7 +3459,7 @@ static void disas_sparc_insn(DisasContext * dc)
3528 int l1; 3459 int l1;
3529 3460
3530 rs1 = GET_FIELD(insn, 13, 17); 3461 rs1 = GET_FIELD(insn, 13, 17);
3531 - gen_movl_reg_T0(rs1); 3462 + gen_movl_reg_TN(rs1, cpu_T[0]);
3532 3463
3533 l1 = gen_new_label(); 3464 l1 = gen_new_label();
3534 3465
@@ -3536,12 +3467,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3536,12 +3467,12 @@ static void disas_sparc_insn(DisasContext * dc)
3536 tcg_const_tl(0), l1); 3467 tcg_const_tl(0), l1);
3537 if (IS_IMM) { /* immediate */ 3468 if (IS_IMM) { /* immediate */
3538 rs2 = GET_FIELD_SPs(insn, 0, 9); 3469 rs2 = GET_FIELD_SPs(insn, 0, 9);
3539 - gen_movl_simm_T1(rs2); 3470 + tcg_gen_movi_tl(cpu_T[1], (int)rs2);
3540 } else { 3471 } else {
3541 rs2 = GET_FIELD_SP(insn, 0, 4); 3472 rs2 = GET_FIELD_SP(insn, 0, 4);
3542 - gen_movl_reg_T1(rs2); 3473 + gen_movl_reg_TN(rs2, cpu_T[1]);
3543 } 3474 }
3544 - gen_movl_T1_reg(rd); 3475 + gen_movl_TN_reg(rd, cpu_T[1]);
3545 gen_set_label(l1); 3476 gen_set_label(l1);
3546 break; 3477 break;
3547 } 3478 }
@@ -3574,34 +3505,34 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3574,34 +3505,34 @@ static void disas_sparc_insn(DisasContext * dc)
3574 // XXX 3505 // XXX
3575 goto illegal_insn; 3506 goto illegal_insn;
3576 case 0x010: /* VIS I array8 */ 3507 case 0x010: /* VIS I array8 */
3577 - gen_movl_reg_T0(rs1);  
3578 - gen_movl_reg_T1(rs2); 3508 + gen_movl_reg_TN(rs1, cpu_T[0]);
  3509 + gen_movl_reg_TN(rs2, cpu_T[1]);
3579 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], 3510 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3580 cpu_T[1]); 3511 cpu_T[1]);
3581 - gen_movl_T0_reg(rd); 3512 + gen_movl_TN_reg(rd, cpu_T[0]);
3582 break; 3513 break;
3583 case 0x012: /* VIS I array16 */ 3514 case 0x012: /* VIS I array16 */
3584 - gen_movl_reg_T0(rs1);  
3585 - gen_movl_reg_T1(rs2); 3515 + gen_movl_reg_TN(rs1, cpu_T[0]);
  3516 + gen_movl_reg_TN(rs2, cpu_T[1]);
3586 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], 3517 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3587 cpu_T[1]); 3518 cpu_T[1]);
3588 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1); 3519 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1);
3589 - gen_movl_T0_reg(rd); 3520 + gen_movl_TN_reg(rd, cpu_T[0]);
3590 break; 3521 break;
3591 case 0x014: /* VIS I array32 */ 3522 case 0x014: /* VIS I array32 */
3592 - gen_movl_reg_T0(rs1);  
3593 - gen_movl_reg_T1(rs2); 3523 + gen_movl_reg_TN(rs1, cpu_T[0]);
  3524 + gen_movl_reg_TN(rs2, cpu_T[1]);
3594 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], 3525 tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
3595 cpu_T[1]); 3526 cpu_T[1]);
3596 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); 3527 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
3597 - gen_movl_T0_reg(rd); 3528 + gen_movl_TN_reg(rd, cpu_T[0]);
3598 break; 3529 break;
3599 case 0x018: /* VIS I alignaddr */ 3530 case 0x018: /* VIS I alignaddr */
3600 - gen_movl_reg_T0(rs1);  
3601 - gen_movl_reg_T1(rs2); 3531 + gen_movl_reg_TN(rs1, cpu_T[0]);
  3532 + gen_movl_reg_TN(rs2, cpu_T[1]);
3602 tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0], 3533 tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0],
3603 cpu_T[1]); 3534 cpu_T[1]);
3604 - gen_movl_T0_reg(rd); 3535 + gen_movl_TN_reg(rd, cpu_T[0]);
3605 break; 3536 break;
3606 case 0x019: /* VIS II bmask */ 3537 case 0x019: /* VIS II bmask */
3607 case 0x01a: /* VIS I alignaddrl */ 3538 case 0x01a: /* VIS I alignaddrl */
@@ -3964,7 +3895,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3964,7 +3895,7 @@ static void disas_sparc_insn(DisasContext * dc)
3964 } else if (xop == 0x39) { /* V9 return */ 3895 } else if (xop == 0x39) { /* V9 return */
3965 rs1 = GET_FIELD(insn, 13, 17); 3896 rs1 = GET_FIELD(insn, 13, 17);
3966 save_state(dc); 3897 save_state(dc);
3967 - gen_movl_reg_T0(rs1); 3898 + gen_movl_reg_TN(rs1, cpu_T[0]);
3968 if (IS_IMM) { /* immediate */ 3899 if (IS_IMM) { /* immediate */
3969 rs2 = GET_FIELDs(insn, 19, 31); 3900 rs2 = GET_FIELDs(insn, 19, 31);
3970 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); 3901 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
@@ -3973,8 +3904,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3973,8 +3904,8 @@ static void disas_sparc_insn(DisasContext * dc)
3973 #if defined(OPTIM) 3904 #if defined(OPTIM)
3974 if (rs2) { 3905 if (rs2) {
3975 #endif 3906 #endif
3976 - gen_movl_reg_T1(rs2);  
3977 - gen_op_add_T1_T0(); 3907 + gen_movl_reg_TN(rs2, cpu_T[1]);
  3908 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3978 #if defined(OPTIM) 3909 #if defined(OPTIM)
3979 } 3910 }
3980 #endif 3911 #endif
@@ -3988,7 +3919,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3988,7 +3919,7 @@ static void disas_sparc_insn(DisasContext * dc)
3988 #endif 3919 #endif
3989 } else { 3920 } else {
3990 rs1 = GET_FIELD(insn, 13, 17); 3921 rs1 = GET_FIELD(insn, 13, 17);
3991 - gen_movl_reg_T0(rs1); 3922 + gen_movl_reg_TN(rs1, cpu_T[0]);
3992 if (IS_IMM) { /* immediate */ 3923 if (IS_IMM) { /* immediate */
3993 rs2 = GET_FIELDs(insn, 19, 31); 3924 rs2 = GET_FIELDs(insn, 19, 31);
3994 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); 3925 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
@@ -3997,8 +3928,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3997,8 +3928,8 @@ static void disas_sparc_insn(DisasContext * dc)
3997 #if defined(OPTIM) 3928 #if defined(OPTIM)
3998 if (rs2) { 3929 if (rs2) {
3999 #endif 3930 #endif
4000 - gen_movl_reg_T1(rs2);  
4001 - gen_op_add_T1_T0(); 3931 + gen_movl_reg_TN(rs2, cpu_T[1]);
  3932 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4002 #if defined(OPTIM) 3933 #if defined(OPTIM)
4003 } 3934 }
4004 #endif 3935 #endif
@@ -4008,7 +3939,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4008,7 +3939,7 @@ static void disas_sparc_insn(DisasContext * dc)
4008 { 3939 {
4009 if (rd != 0) { 3940 if (rd != 0) {
4010 tcg_gen_movi_tl(cpu_T[1], dc->pc); 3941 tcg_gen_movi_tl(cpu_T[1], dc->pc);
4011 - gen_movl_T1_reg(rd); 3942 + gen_movl_TN_reg(rd, cpu_T[1]);
4012 } 3943 }
4013 gen_mov_pc_npc(dc); 3944 gen_mov_pc_npc(dc);
4014 gen_op_check_align_T0_3(); 3945 gen_op_check_align_T0_3();
@@ -4035,12 +3966,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4035,12 +3966,12 @@ static void disas_sparc_insn(DisasContext * dc)
4035 case 0x3c: /* save */ 3966 case 0x3c: /* save */
4036 save_state(dc); 3967 save_state(dc);
4037 tcg_gen_helper_0_0(helper_save); 3968 tcg_gen_helper_0_0(helper_save);
4038 - gen_movl_T0_reg(rd); 3969 + gen_movl_TN_reg(rd, cpu_T[0]);
4039 break; 3970 break;
4040 case 0x3d: /* restore */ 3971 case 0x3d: /* restore */
4041 save_state(dc); 3972 save_state(dc);
4042 tcg_gen_helper_0_0(helper_restore); 3973 tcg_gen_helper_0_0(helper_restore);
4043 - gen_movl_T0_reg(rd); 3974 + gen_movl_TN_reg(rd, cpu_T[0]);
4044 break; 3975 break;
4045 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) 3976 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4046 case 0x3e: /* V9 done/retry */ 3977 case 0x3e: /* V9 done/retry */
@@ -4078,11 +4009,11 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4078,11 +4009,11 @@ static void disas_sparc_insn(DisasContext * dc)
4078 unsigned int xop = GET_FIELD(insn, 7, 12); 4009 unsigned int xop = GET_FIELD(insn, 7, 12);
4079 rs1 = GET_FIELD(insn, 13, 17); 4010 rs1 = GET_FIELD(insn, 13, 17);
4080 save_state(dc); 4011 save_state(dc);
4081 - gen_movl_reg_T0(rs1); 4012 + gen_movl_reg_TN(rs1, cpu_T[0]);
4082 if (xop == 0x3c || xop == 0x3e) 4013 if (xop == 0x3c || xop == 0x3e)
4083 { 4014 {
4084 rs2 = GET_FIELD(insn, 27, 31); 4015 rs2 = GET_FIELD(insn, 27, 31);
4085 - gen_movl_reg_T1(rs2); 4016 + gen_movl_reg_TN(rs2, cpu_T[1]);
4086 } 4017 }
4087 else if (IS_IMM) { /* immediate */ 4018 else if (IS_IMM) { /* immediate */
4088 rs2 = GET_FIELDs(insn, 19, 31); 4019 rs2 = GET_FIELDs(insn, 19, 31);
@@ -4092,8 +4023,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4092,8 +4023,8 @@ static void disas_sparc_insn(DisasContext * dc)
4092 #if defined(OPTIM) 4023 #if defined(OPTIM)
4093 if (rs2 != 0) { 4024 if (rs2 != 0) {
4094 #endif 4025 #endif
4095 - gen_movl_reg_T1(rs2);  
4096 - gen_op_add_T1_T0(); 4026 + gen_movl_reg_TN(rs2, cpu_T[1]);
  4027 + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4097 #if defined(OPTIM) 4028 #if defined(OPTIM)
4098 } 4029 }
4099 #endif 4030 #endif
@@ -4125,7 +4056,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4125,7 +4056,7 @@ static void disas_sparc_insn(DisasContext * dc)
4125 tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx); 4056 tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx);
4126 tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64); 4057 tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
4127 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffffffULL); 4058 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffffffULL);
4128 - gen_movl_T0_reg(rd + 1); 4059 + gen_movl_TN_reg(rd + 1, cpu_T[0]);
4129 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); 4060 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4130 tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64); 4061 tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
4131 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffffffffULL); 4062 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffffffffULL);
@@ -4147,7 +4078,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4147,7 +4078,7 @@ static void disas_sparc_insn(DisasContext * dc)
4147 break; 4078 break;
4148 case 0x0f: /* swap register with memory. Also atomically */ 4079 case 0x0f: /* swap register with memory. Also atomically */
4149 gen_op_check_align_T0_3(); 4080 gen_op_check_align_T0_3();
4150 - gen_movl_reg_T1(rd); 4081 + gen_movl_reg_TN(rd, cpu_T[1]);
4151 ABI32_MASK(cpu_T[0]); 4082 ABI32_MASK(cpu_T[0]);
4152 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx); 4083 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
4153 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); 4084 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
@@ -4194,7 +4125,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4194,7 +4125,7 @@ static void disas_sparc_insn(DisasContext * dc)
4194 goto illegal_insn; 4125 goto illegal_insn;
4195 gen_op_check_align_T0_7(); 4126 gen_op_check_align_T0_7();
4196 gen_ldda_asi(insn); 4127 gen_ldda_asi(insn);
4197 - gen_movl_T0_reg(rd + 1); 4128 + gen_movl_TN_reg(rd + 1, cpu_T[0]);
4198 break; 4129 break;
4199 case 0x19: /* load signed byte alternate */ 4130 case 0x19: /* load signed byte alternate */
4200 #ifndef TARGET_SPARC64 4131 #ifndef TARGET_SPARC64
@@ -4232,7 +4163,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4232,7 +4163,7 @@ static void disas_sparc_insn(DisasContext * dc)
4232 goto priv_insn; 4163 goto priv_insn;
4233 #endif 4164 #endif
4234 gen_op_check_align_T0_3(); 4165 gen_op_check_align_T0_3();
4235 - gen_movl_reg_T1(rd); 4166 + gen_movl_reg_TN(rd, cpu_T[1]);
4236 gen_swap_asi(insn); 4167 gen_swap_asi(insn);
4237 break; 4168 break;
4238 4169
@@ -4286,7 +4217,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4286,7 +4217,7 @@ static void disas_sparc_insn(DisasContext * dc)
4286 default: 4217 default:
4287 goto illegal_insn; 4218 goto illegal_insn;
4288 } 4219 }
4289 - gen_movl_T1_reg(rd); 4220 + gen_movl_TN_reg(rd, cpu_T[1]);
4290 #ifdef TARGET_SPARC64 4221 #ifdef TARGET_SPARC64
4291 skip_move: ; 4222 skip_move: ;
4292 #endif 4223 #endif
@@ -4326,7 +4257,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4326,7 +4257,7 @@ static void disas_sparc_insn(DisasContext * dc)
4326 } 4257 }
4327 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ 4258 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4328 xop == 0xe || xop == 0x1e) { 4259 xop == 0xe || xop == 0x1e) {
4329 - gen_movl_reg_T1(rd); 4260 + gen_movl_reg_TN(rd, cpu_T[1]);
4330 switch (xop) { 4261 switch (xop) {
4331 case 0x4: /* store word */ 4262 case 0x4: /* store word */
4332 gen_op_check_align_T0_3(); 4263 gen_op_check_align_T0_3();
@@ -4359,7 +4290,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4359,7 +4290,7 @@ static void disas_sparc_insn(DisasContext * dc)
4359 #else /* __i386__ */ 4290 #else /* __i386__ */
4360 gen_op_check_align_T0_7(); 4291 gen_op_check_align_T0_7();
4361 flush_T2(dc); 4292 flush_T2(dc);
4362 - gen_movl_reg_T2(rd + 1); 4293 + gen_movl_reg_TN(rd + 1, cpu_T[2]);
4363 gen_op_ldst(std); 4294 gen_op_ldst(std);
4364 #endif /* __i386__ */ 4295 #endif /* __i386__ */
4365 break; 4296 break;
@@ -4497,12 +4428,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4497,12 +4428,12 @@ static void disas_sparc_insn(DisasContext * dc)
4497 case 0x3c: /* V9 casa */ 4428 case 0x3c: /* V9 casa */
4498 gen_op_check_align_T0_3(); 4429 gen_op_check_align_T0_3();
4499 gen_cas_asi(insn, rd); 4430 gen_cas_asi(insn, rd);
4500 - gen_movl_T1_reg(rd); 4431 + gen_movl_TN_reg(rd, cpu_T[1]);
4501 break; 4432 break;
4502 case 0x3e: /* V9 casxa */ 4433 case 0x3e: /* V9 casxa */
4503 gen_op_check_align_T0_7(); 4434 gen_op_check_align_T0_7();
4504 gen_casx_asi(insn, rd); 4435 gen_casx_asi(insn, rd);
4505 - gen_movl_T1_reg(rd); 4436 + gen_movl_TN_reg(rd, cpu_T[1]);
4506 break; 4437 break;
4507 #else 4438 #else
4508 case 0x34: /* stc */ 4439 case 0x34: /* stc */
@@ -4536,13 +4467,13 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4536,13 +4467,13 @@ static void disas_sparc_insn(DisasContext * dc)
4536 return; 4467 return;
4537 illegal_insn: 4468 illegal_insn:
4538 save_state(dc); 4469 save_state(dc);
4539 - gen_op_exception(TT_ILL_INSN); 4470 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4540 dc->is_br = 1; 4471 dc->is_br = 1;
4541 return; 4472 return;
4542 #if !defined(CONFIG_USER_ONLY) 4473 #if !defined(CONFIG_USER_ONLY)
4543 priv_insn: 4474 priv_insn:
4544 save_state(dc); 4475 save_state(dc);
4545 - gen_op_exception(TT_PRIV_INSN); 4476 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4546 dc->is_br = 1; 4477 dc->is_br = 1;
4547 return; 4478 return;
4548 nfpu_insn: 4479 nfpu_insn:
@@ -4561,7 +4492,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4561,7 +4492,7 @@ static void disas_sparc_insn(DisasContext * dc)
4561 #ifndef TARGET_SPARC64 4492 #ifndef TARGET_SPARC64
4562 ncp_insn: 4493 ncp_insn:
4563 save_state(dc); 4494 save_state(dc);
4564 - gen_op_exception(TT_NCP_INSN); 4495 + tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4565 dc->is_br = 1; 4496 dc->is_br = 1;
4566 return; 4497 return;
4567 #endif 4498 #endif
@@ -4634,7 +4565,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, @@ -4634,7 +4565,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4634 /* if single step mode, we generate only one instruction and 4565 /* if single step mode, we generate only one instruction and
4635 generate an exception */ 4566 generate an exception */
4636 if (env->singlestep_enabled) { 4567 if (env->singlestep_enabled) {
4637 - gen_jmp_im(dc->pc); 4568 + tcg_gen_movi_tl(cpu_pc, dc->pc);
4638 tcg_gen_exit_tb(0); 4569 tcg_gen_exit_tb(0);
4639 break; 4570 break;
4640 } 4571 }
@@ -4646,10 +4577,10 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, @@ -4646,10 +4577,10 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4646 if (dc->pc != DYNAMIC_PC && 4577 if (dc->pc != DYNAMIC_PC &&
4647 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { 4578 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4648 /* static PC and NPC: we can use direct chaining */ 4579 /* static PC and NPC: we can use direct chaining */
4649 - gen_branch(dc, dc->pc, dc->npc); 4580 + gen_goto_tb(dc, 0, dc->pc, dc->npc);
4650 } else { 4581 } else {
4651 if (dc->pc != DYNAMIC_PC) 4582 if (dc->pc != DYNAMIC_PC)
4652 - gen_jmp_im(dc->pc); 4583 + tcg_gen_movi_tl(cpu_pc, dc->pc);
4653 save_npc(dc); 4584 save_npc(dc);
4654 tcg_gen_exit_tb(0); 4585 tcg_gen_exit_tb(0);
4655 } 4586 }