Commit 2c6ab8329e870c4e4c00caa2169db421f9b42b86

Authored by bellard
1 parent 675376f2

load/save state support


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@992 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 91 additions and 0 deletions
hw/cirrus_vga.c
... ... @@ -2753,6 +2753,95 @@ static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
2753 2753 cirrus_mmio_writel,
2754 2754 };
2755 2755  
  2756 +/* load/save state */
  2757 +
  2758 +static void cirrus_vga_save(QEMUFile *f, void *opaque)
  2759 +{
  2760 + CirrusVGAState *s = opaque;
  2761 +
  2762 + qemu_put_be32s(f, &s->latch);
  2763 + qemu_put_8s(f, &s->sr_index);
  2764 + qemu_put_buffer(f, s->sr, 256);
  2765 + qemu_put_8s(f, &s->gr_index);
  2766 + qemu_put_8s(f, &s->cirrus_shadow_gr0);
  2767 + qemu_put_8s(f, &s->cirrus_shadow_gr1);
  2768 + qemu_put_buffer(f, s->gr + 2, 254);
  2769 + qemu_put_8s(f, &s->ar_index);
  2770 + qemu_put_buffer(f, s->ar, 21);
  2771 + qemu_put_be32s(f, &s->ar_flip_flop);
  2772 + qemu_put_8s(f, &s->cr_index);
  2773 + qemu_put_buffer(f, s->cr, 256);
  2774 + qemu_put_8s(f, &s->msr);
  2775 + qemu_put_8s(f, &s->fcr);
  2776 + qemu_put_8s(f, &s->st00);
  2777 + qemu_put_8s(f, &s->st01);
  2778 +
  2779 + qemu_put_8s(f, &s->dac_state);
  2780 + qemu_put_8s(f, &s->dac_sub_index);
  2781 + qemu_put_8s(f, &s->dac_read_index);
  2782 + qemu_put_8s(f, &s->dac_write_index);
  2783 + qemu_put_buffer(f, s->dac_cache, 3);
  2784 + qemu_put_buffer(f, s->palette, 768);
  2785 +
  2786 + qemu_put_be32s(f, &s->bank_offset);
  2787 +
  2788 + qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
  2789 + qemu_put_8s(f, &s->cirrus_hidden_dac_data);
  2790 +
  2791 + qemu_put_be32s(f, &s->hw_cursor_x);
  2792 + qemu_put_be32s(f, &s->hw_cursor_y);
  2793 + /* XXX: we do not save the bitblt state - we assume we do not save
  2794 + the state when the blitter is active */
  2795 +}
  2796 +
  2797 +static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
  2798 +{
  2799 + CirrusVGAState *s = opaque;
  2800 +
  2801 + if (version_id != 1)
  2802 + return -EINVAL;
  2803 +
  2804 + qemu_get_be32s(f, &s->latch);
  2805 + qemu_get_8s(f, &s->sr_index);
  2806 + qemu_get_buffer(f, s->sr, 256);
  2807 + qemu_get_8s(f, &s->gr_index);
  2808 + qemu_get_8s(f, &s->cirrus_shadow_gr0);
  2809 + qemu_get_8s(f, &s->cirrus_shadow_gr1);
  2810 + s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
  2811 + s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
  2812 + qemu_get_buffer(f, s->gr + 2, 254);
  2813 + qemu_get_8s(f, &s->ar_index);
  2814 + qemu_get_buffer(f, s->ar, 21);
  2815 + qemu_get_be32s(f, &s->ar_flip_flop);
  2816 + qemu_get_8s(f, &s->cr_index);
  2817 + qemu_get_buffer(f, s->cr, 256);
  2818 + qemu_get_8s(f, &s->msr);
  2819 + qemu_get_8s(f, &s->fcr);
  2820 + qemu_get_8s(f, &s->st00);
  2821 + qemu_get_8s(f, &s->st01);
  2822 +
  2823 + qemu_get_8s(f, &s->dac_state);
  2824 + qemu_get_8s(f, &s->dac_sub_index);
  2825 + qemu_get_8s(f, &s->dac_read_index);
  2826 + qemu_get_8s(f, &s->dac_write_index);
  2827 + qemu_get_buffer(f, s->dac_cache, 3);
  2828 + qemu_get_buffer(f, s->palette, 768);
  2829 +
  2830 + qemu_get_be32s(f, &s->bank_offset);
  2831 +
  2832 + qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
  2833 + qemu_get_8s(f, &s->cirrus_hidden_dac_data);
  2834 +
  2835 + qemu_get_be32s(f, &s->hw_cursor_x);
  2836 + qemu_get_be32s(f, &s->hw_cursor_y);
  2837 +
  2838 + /* force refresh */
  2839 + s->graphic_mode = -1;
  2840 + cirrus_update_bank_ptr(s, 0);
  2841 + cirrus_update_bank_ptr(s, 1);
  2842 + return 0;
  2843 +}
  2844 +
2756 2845 /***************************************
2757 2846 *
2758 2847 * initialize
... ... @@ -2862,6 +2951,8 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
2862 2951 s->get_resolution = cirrus_get_resolution;
2863 2952 s->cursor_invalidate = cirrus_cursor_invalidate;
2864 2953 s->cursor_draw_line = cirrus_cursor_draw_line;
  2954 +
  2955 + register_savevm("cirrus_vga", 0, 1, cirrus_vga_save, cirrus_vga_load, s);
2865 2956 }
2866 2957  
2867 2958 /***************************************
... ...