Commit 2ae72bce02abe962dc0c11d40f2f872378ccd5de
1 parent
221bb2d5
Correct 32bit carry flag for add instruction (Igor Kovalenko)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5017 c046a42c-6fe2-441c-8c8c-71466251a162
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8 additions
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5 deletions
target-sparc/translate.c
| @@ -349,16 +349,19 @@ static inline void gen_cc_NZ_xcc(TCGv dst) | @@ -349,16 +349,19 @@ static inline void gen_cc_NZ_xcc(TCGv dst) | ||
| 349 | */ | 349 | */ |
| 350 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) | 350 | static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
| 351 | { | 351 | { |
| 352 | - TCGv r_temp; | 352 | + TCGv r_temp1, r_temp2; |
| 353 | int l1; | 353 | int l1; |
| 354 | 354 | ||
| 355 | l1 = gen_new_label(); | 355 | l1 = gen_new_label(); |
| 356 | - r_temp = tcg_temp_new(TCG_TYPE_TL); | ||
| 357 | - tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); | ||
| 358 | - tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | 356 | + r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
| 357 | + r_temp2 = tcg_temp_new(TCG_TYPE_TL); | ||
| 358 | + tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL); | ||
| 359 | + tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL); | ||
| 360 | + tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); | ||
| 359 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); | 361 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
| 360 | gen_set_label(l1); | 362 | gen_set_label(l1); |
| 361 | - tcg_temp_free(r_temp); | 363 | + tcg_temp_free(r_temp1); |
| 364 | + tcg_temp_free(r_temp2); | ||
| 362 | } | 365 | } |
| 363 | 366 | ||
| 364 | #ifdef TARGET_SPARC64 | 367 | #ifdef TARGET_SPARC64 |