gwj / at91sam9263 · Commits

Commit 2ac711791b2e4aabc5e4046b7428727828c705eb

Authored by Paul Brook
1 parent e612a1f7

Replace cpu_abort with hw_error 

Signed-off-by: Paul Brook <paul@codesourcery.com>
Inline Side-by-side
Showing 47 changed files with 180 additions and 262 deletions
hw/an5206.c
  View file @2ac7117
... ... @@ -41,7 +41,7 @@ static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
41 41 cpu_model = "m5206";
42 42 env = cpu_init(cpu_model);
43 43 if (!env) {
44   - cpu_abort(env, "Unable to find m68k CPU definition\n");
  44 + hw_error("Unable to find m68k CPU definition\n");
45 45 }
46 46  
47 47 /* Initialize CPU registers. */
... ...
hw/arm_gic.c
  View file @2ac7117
... ... @@ -343,7 +343,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
343 343 }
344 344 return res;
345 345 bad_reg:
346   - cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n", (int)offset);
  346 + hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
347 347 return 0;
348 348 }
349 349  
... ... @@ -505,7 +505,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
505 505 gic_update(s);
506 506 return;
507 507 bad_reg:
508   - cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n", (int)offset);
  508 + hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
509 509 }
510 510  
511 511 static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
... ... @@ -587,8 +587,7 @@ static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
587 587 case 0x18: /* Highest Pending Interrupt */
588 588 return s->current_pending[cpu];
589 589 default:
590   - cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n",
591   - (int)offset);
  590 + hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
592 591 return 0;
593 592 }
594 593 }
... ... @@ -609,8 +608,7 @@ static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
609 608 case 0x10: /* End Of Interrupt */
610 609 return gic_complete_irq(s, cpu, value & 0x3ff);
611 610 default:
612   - cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n",
613   - (int)offset);
  611 + hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
614 612 return;
615 613 }
616 614 gic_update(s);
... ...
hw/arm_pic.c
  View file @2ac7117
... ... @@ -39,7 +39,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
39 39 cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
40 40 break;
41 41 default:
42   - cpu_abort(env, "arm_pic_cpu_handler: Bad interrput line %d\n", irq);
  42 + hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq);
43 43 }
44 44 }
45 45  
... ...
hw/arm_timer.c
  View file @2ac7117
... ... @@ -62,8 +62,7 @@ static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
62 62 return 0;
63 63 return s->int_level;
64 64 default:
65   - cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
66   - (int)offset);
  65 + hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
67 66 return 0;
68 67 }
69 68 }
... ... @@ -130,8 +129,7 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset,
130 129 arm_timer_recalibrate(s, 0);
131 130 break;
132 131 default:
133   - cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
134   - (int)offset);
  132 + hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
135 133 }
136 134 arm_timer_update(s);
137 135 }
... ... @@ -290,8 +288,9 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
290 288  
291 289 /* ??? Don't know the PrimeCell ID for this device. */
292 290 n = offset >> 8;
293   - if (n > 3)
294   - cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
  291 + if (n > 3) {
  292 + hw_error("sp804_read: Bad timer %d\n", n);
  293 + }
295 294  
296 295 return arm_timer_read(s->timer[n], offset & 0xff);
297 296 }
... ... @@ -303,8 +302,9 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset,
303 302 int n;
304 303  
305 304 n = offset >> 8;
306   - if (n > 3)
307   - cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
  305 + if (n > 3) {
  306 + hw_error("sp804_write: Bad timer %d\n", n);
  307 + }
308 308  
309 309 arm_timer_write(s->timer[n], offset & 0xff, value);
310 310 }
... ...
hw/armv7m_nvic.c
  View file @2ac7117
... ... @@ -102,7 +102,7 @@ int armv7m_nvic_acknowledge_irq(void *opaque)
102 102  
103 103 irq = gic_acknowledge_irq(s->gic, 0);
104 104 if (irq == 1023)
105   - cpu_abort(cpu_single_env, "Interrupt but no vector\n");
  105 + hw_error("Interrupt but no vector\n");
106 106 if (irq >= 32)
107 107 irq -= 16;
108 108 return irq;
... ... @@ -221,8 +221,7 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
221 221 return val;
222 222 case 0xd28: /* Configurable Fault Status. */
223 223 /* TODO: Implement Fault Status. */
224   - cpu_abort(cpu_single_env,
225   - "Not implemented: Configurable Fault Status.");
  224 + hw_error("Not implemented: Configurable Fault Status.");
226 225 return 0;
227 226 case 0xd2c: /* Hard Fault Status. */
228 227 case 0xd30: /* Debug Fault Status. */
... ... @@ -260,7 +259,7 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
260 259 /* TODO: Implement debug registers. */
261 260 default:
262 261 bad_reg:
263   - cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
  262 + hw_error("NVIC: Bad read offset 0x%x\n", offset);
264 263 }
265 264 }
266 265  
... ... @@ -324,10 +323,10 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
324 323 case 0xd0c: /* Application Interrupt/Reset Control. */
325 324 if ((value >> 16) == 0x05fa) {
326 325 if (value & 2) {
327   - cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
  326 + hw_error("VECTCLRACTIVE not implemented");
328 327 }
329 328 if (value & 5) {
330   - cpu_abort(cpu_single_env, "System reset");
  329 + hw_error("System reset");
331 330 }
332 331 }
333 332 break;
... ... @@ -362,7 +361,7 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
362 361 goto bad_reg;
363 362 default:
364 363 bad_reg:
365   - cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
  364 + hw_error("NVIC: Bad write offset 0x%x\n", offset);
366 365 }
367 366 }
368 367  
... ... @@ -402,7 +401,7 @@ qemu_irq *armv7m_nvic_init(CPUState *env)
402 401 s->gic->nvic = s;
403 402 s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
404 403 if (env->v7m.nvic)
405   - cpu_abort(env, "CPU can only have one NVIC\n");
  404 + hw_error("CPU can only have one NVIC\n");
406 405 env->v7m.nvic = s;
407 406 register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
408 407 return s->gic->in;
... ...
hw/cbus.c
  View file @2ac7117
... ... @@ -63,8 +63,7 @@ static void cbus_io(struct cbus_priv_s *s)
63 63 s->slave[s->addr]->io(s->slave[s->addr]->opaque,
64 64 s->rw, s->reg, &s->val);
65 65 else
66   - cpu_abort(cpu_single_env, "%s: bad slave address %i\n",
67   - __FUNCTION__, s->addr);
  66 + hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
68 67 }
69 68  
70 69 static void cbus_cycle(struct cbus_priv_s *s)
... ... @@ -301,8 +300,7 @@ static inline uint16_t retu_read(struct cbus_retu_s *s, int reg)
301 300 return 0x0000;
302 301  
303 302 default:
304   - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
305   - __FUNCTION__, reg);
  303 + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
306 304 }
307 305 }
308 306  
... ... @@ -375,8 +373,7 @@ static inline void retu_write(struct cbus_retu_s *s, int reg, uint16_t val)
375 373 break;
376 374  
377 375 default:
378   - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
379   - __FUNCTION__, reg);
  376 + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
380 377 }
381 378 }
382 379  
... ... @@ -542,8 +539,7 @@ static inline uint16_t tahvo_read(struct cbus_tahvo_s *s, int reg)
542 539 return 0x0000;
543 540  
544 541 default:
545   - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
546   - __FUNCTION__, reg);
  542 + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
547 543 }
548 544 }
549 545  
... ... @@ -593,8 +589,7 @@ static inline void tahvo_write(struct cbus_tahvo_s *s, int reg, uint16_t val)
593 589 break;
594 590  
595 591 default:
596   - cpu_abort(cpu_single_env, "%s: bad register %02x\n",
597   - __FUNCTION__, reg);
  592 + hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
598 593 }
599 594 }
600 595  
... ...
hw/etraxfs_dma.c
  View file @2ac7117
... ... @@ -562,10 +562,7 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
562 562  
563 563 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
564 564 {
565   - struct fs_dma_ctrl *ctrl = opaque;
566   - CPUState *env = ctrl->env;
567   - cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
568   - addr);
  565 + hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
569 566 return 0;
570 567 }
571 568  
... ... @@ -600,10 +597,7 @@ dma_readl (void *opaque, target_phys_addr_t addr)
600 597 static void
601 598 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
602 599 {
603   - struct fs_dma_ctrl *ctrl = opaque;
604   - CPUState *env = ctrl->env;
605   - cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
606   - addr);
  600 + hw_error("Unsupported short access. reg=" TARGET_FMT_plx "\n", addr);
607 601 }
608 602  
609 603 static void
... ...
hw/etraxfs_pic.c
  View file @2ac7117
... ... @@ -148,8 +148,7 @@ static void nmi_handler(void *opaque, int irq, int level)
148 148  
149 149 static void guru_handler(void *opaque, int irq, int level)
150 150 {
151   - struct fs_pic_state *fs = (void *)opaque;
152   - cpu_abort(fs->env, "%s unsupported exception\n", __func__);
  151 + hw_error("%s unsupported exception\n", __func__);
153 152 }
154 153  
155 154 struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
... ...
hw/integratorcp.c
  View file @2ac7117
... ... @@ -63,7 +63,7 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
63 63 }
64 64 case 6: /* CM_LMBUSCNT */
65 65 /* ??? High frequency timer. */
66   - cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
  66 + hw_error("integratorcm_read: CM_LMBUSCNT");
67 67 case 7: /* CM_AUXOSC */
68 68 return s->cm_auxosc;
69 69 case 8: /* CM_SDRAM */
... ... @@ -72,7 +72,7 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
72 72 return s->cm_init;
73 73 case 10: /* CM_REFCT */
74 74 /* ??? High frequency timer. */
75   - cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
  75 + hw_error("integratorcm_read: CM_REFCT");
76 76 case 12: /* CM_FLAGS */
77 77 return s->cm_flags;
78 78 case 14: /* CM_NVFLAGS */
... ... @@ -98,8 +98,8 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
98 98 /* ??? Voltage control unimplemented. */
99 99 return 0;
100 100 default:
101   - cpu_abort (cpu_single_env,
102   - "integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
  101 + hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
  102 + (int)offset);
103 103 return 0;
104 104 }
105 105 }
... ... @@ -117,7 +117,7 @@ static void integratorcm_do_remap(integratorcm_state *s, int flash)
117 117 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
118 118 {
119 119 if (value & 8) {
120   - cpu_abort(cpu_single_env, "Board reset\n");
  120 + hw_error("Board reset\n");
121 121 }
122 122 if ((s->cm_init ^ value) & 4) {
123 123 integratorcm_do_remap(s, (value & 4) == 0);
... ... @@ -133,7 +133,7 @@ static void integratorcm_update(integratorcm_state *s)
133 133 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
134 134 are active. */
135 135 if (s->int_level & (s->irq_enabled | s->fiq_enabled))
136   - cpu_abort(cpu_single_env, "Core module interrupt\n");
  136 + hw_error("Core module interrupt\n");
137 137 }
138 138  
139 139 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
... ... @@ -205,8 +205,8 @@ static void integratorcm_write(void *opaque, target_phys_addr_t offset,
205 205 /* ??? Voltage control unimplemented. */
206 206 break;
207 207 default:
208   - cpu_abort (cpu_single_env,
209   - "integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
  208 + hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
  209 + (int)offset);
210 210 break;
211 211 }
212 212 }
... ... @@ -401,8 +401,7 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
401 401 case 3: /* CP_DECODE */
402 402 return 0x11;
403 403 default:
404   - cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
405   - (int)offset);
  404 + hw_error("icp_control_read: Bad offset %x\n", (int)offset);
406 405 return 0;
407 406 }
408 407 }
... ... @@ -417,8 +416,7 @@ static void icp_control_write(void *opaque, target_phys_addr_t offset,
417 416 /* Nothing interesting implemented yet. */
418 417 break;
419 418 default:
420   - cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
421   - (int)offset);
  419 + hw_error("icp_control_write: Bad offset %x\n", (int)offset);
422 420 }
423 421 }
424 422 static CPUReadMemoryFunc *icp_control_readfn[] = {
... ...
hw/mcf5206.c
  View file @2ac7117
... ... @@ -61,11 +61,9 @@ static void m5206_timer_recalibrate(m5206_timer_state *s)
61 61 prescale *= 16;
62 62  
63 63 if (mode == 3 || mode == 0)
64   - cpu_abort(cpu_single_env,
65   - "m5206_timer: mode %d not implemented\n", mode);
  64 + hw_error("m5206_timer: mode %d not implemented\n", mode);
66 65 if ((s->tmr & TMR_FRR) == 0)
67   - cpu_abort(cpu_single_env,
68   - "m5206_timer: free running mode not implemented\n");
  66 + hw_error("m5206_timer: free running mode not implemented\n");
69 67  
70 68 /* Assume 66MHz system clock. */
71 69 ptimer_set_freq(s->timer, 66000000 / prescale);
... ... @@ -296,7 +294,7 @@ static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
296 294 case 0x170: return s->uivr[0];
297 295 case 0x1b0: return s->uivr[1];
298 296 }
299   - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
  297 + hw_error("Bad MBAR read offset 0x%x", (int)offset);
300 298 return 0;
301 299 }
302 300  
... ... @@ -350,7 +348,7 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
350 348 s->uivr[1] = value;
351 349 break;
352 350 default:
353   - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
  351 + hw_error("Bad MBAR write offset 0x%x", (int)offset);
354 352 break;
355 353 }
356 354 }
... ... @@ -377,7 +375,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
377 375 m5206_mbar_state *s = (m5206_mbar_state *)opaque;
378 376 offset &= 0x3ff;
379 377 if (offset > 0x200) {
380   - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
  378 + hw_error("Bad MBAR read offset 0x%x", (int)offset);
381 379 }
382 380 if (m5206_mbar_width[offset >> 2] > 1) {
383 381 uint16_t val;
... ... @@ -396,7 +394,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
396 394 int width;
397 395 offset &= 0x3ff;
398 396 if (offset > 0x200) {
399   - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
  397 + hw_error("Bad MBAR read offset 0x%x", (int)offset);
400 398 }
401 399 width = m5206_mbar_width[offset >> 2];
402 400 if (width > 2) {
... ... @@ -420,7 +418,7 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
420 418 int width;
421 419 offset &= 0x3ff;
422 420 if (offset > 0x200) {
423   - cpu_abort(cpu_single_env, "Bad MBAR read offset 0x%x", (int)offset);
  421 + hw_error("Bad MBAR read offset 0x%x", (int)offset);
424 422 }
425 423 width = m5206_mbar_width[offset >> 2];
426 424 if (width < 4) {
... ... @@ -444,7 +442,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
444 442 int width;
445 443 offset &= 0x3ff;
446 444 if (offset > 0x200) {
447   - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
  445 + hw_error("Bad MBAR write offset 0x%x", (int)offset);
448 446 }
449 447 width = m5206_mbar_width[offset >> 2];
450 448 if (width > 1) {
... ... @@ -468,7 +466,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
468 466 int width;
469 467 offset &= 0x3ff;
470 468 if (offset > 0x200) {
471   - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
  469 + hw_error("Bad MBAR write offset 0x%x", (int)offset);
472 470 }
473 471 width = m5206_mbar_width[offset >> 2];
474 472 if (width > 2) {
... ... @@ -496,7 +494,7 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
496 494 int width;
497 495 offset &= 0x3ff;
498 496 if (offset > 0x200) {
499   - cpu_abort(cpu_single_env, "Bad MBAR write offset 0x%x", (int)offset);
  497 + hw_error("Bad MBAR write offset 0x%x", (int)offset);
500 498 }
501 499 width = m5206_mbar_width[offset >> 2];
502 500 if (width < 4) {
... ...
hw/mcf5208.c
  View file @2ac7117
... ... @@ -89,8 +89,7 @@ static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
89 89 case 4:
90 90 break;
91 91 default:
92   - cpu_abort(cpu_single_env, "m5208_timer_write: Bad offset 0x%x\n",
93   - (int)offset);
  92 + hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
94 93 break;
95 94 }
96 95 m5208_timer_update(s);
... ... @@ -114,8 +113,7 @@ static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
114 113 case 4:
115 114 return ptimer_get_count(s->timer);
116 115 default:
117   - cpu_abort(cpu_single_env, "m5208_timer_read: Bad offset 0x%x\n",
118   - (int)addr);
  116 + hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
119 117 return 0;
120 118 }
121 119 }
... ... @@ -148,8 +146,7 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
148 146 return 0;
149 147  
150 148 default:
151   - cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
152   - (int)addr);
  149 + hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
153 150 return 0;
154 151 }
155 152 }
... ... @@ -157,8 +154,7 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
157 154 static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
158 155 uint32_t value)
159 156 {
160   - cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
161   - (int)addr);
  157 + hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
162 158 }
163 159  
164 160 static CPUReadMemoryFunc *m5208_sys_readfn[] = {
... ...
hw/mcf_fec.c
  View file @2ac7117
... ... @@ -246,8 +246,7 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
246 246 case 0x184: return s->etdsr;
247 247 case 0x188: return s->emrbr;
248 248 default:
249   - cpu_abort(cpu_single_env, "mcf_fec_read: Bad address 0x%x\n",
250   - (int)addr);
  249 + hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
251 250 return 0;
252 251 }
253 252 }
... ... @@ -343,8 +342,7 @@ static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
343 342 s->emrbr = value & 0x7f0;
344 343 break;
345 344 default:
346   - cpu_abort(cpu_single_env, "mcf_fec_write Bad address 0x%x\n",
347   - (int)addr);
  345 + hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
348 346 }
349 347 mcf_fec_update(s);
350 348 }
... ...
hw/mcf_intc.c
  View file @2ac7117
... ... @@ -67,7 +67,7 @@ static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
67 67 case 0xe1: case 0xe2: case 0xe3: case 0xe4:
68 68 case 0xe5: case 0xe6: case 0xe7:
69 69 /* LnIACK */
70   - cpu_abort(cpu_single_env, "mcf_intc_read: LnIACK not implemented\n");
  70 + hw_error("mcf_intc_read: LnIACK not implemented\n");
71 71 default:
72 72 return 0;
73 73 }
... ... @@ -99,8 +99,7 @@ static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
99 99 s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
100 100 break;
101 101 default:
102   - cpu_abort(cpu_single_env, "mcf_intc_write: Bad write offset %d\n",
103   - offset);
  102 + hw_error("mcf_intc_write: Bad write offset %d\n", offset);
104 103 break;
105 104 }
106 105 mcf_intc_update(s);
... ...
hw/mpcore.c
  View file @2ac7117
... ... @@ -195,8 +195,7 @@ static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
195 195 return mpcore_timer_read(&s->timer[id], offset & 0xf);
196 196 }
197 197 bad_reg:
198   - cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
199   - (int)offset);
  198 + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
200 199 return 0;
201 200 }
202 201  
... ... @@ -241,8 +240,7 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
241 240 }
242 241 return;
243 242 bad_reg:
244   - cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
245   - (int)offset);
  243 + hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
246 244 }
247 245  
248 246 static CPUReadMemoryFunc *mpcore_priv_readfn[] = {
... ...
hw/musicpal.c
  View file @2ac7117
... ... @@ -875,7 +875,7 @@ static void lcd_refresh(void *opaque)
875 875 LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
876 876 rgb_to_pixel32bgr : rgb_to_pixel32))
877 877 default:
878   - cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
  878 + hw_error("unsupported colour depth %i\n",
879 879 ds_get_bits_per_pixel(s->ds));
880 880 }
881 881  
... ...
hw/nand.c
  View file @2ac7117
... ... @@ -445,8 +445,7 @@ struct nand_flash_s *nand_init(int manf_id, int chip_id)
445 445 int index;
446 446  
447 447 if (nand_flash_ids[chip_id].size == 0) {
448   - cpu_abort(cpu_single_env, "%s: Unsupported NAND chip ID.\n",
449   - __FUNCTION__);
  448 + hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
450 449 }
451 450  
452 451 s = (struct nand_flash_s *) qemu_mallocz(sizeof(struct nand_flash_s));
... ... @@ -475,8 +474,7 @@ struct nand_flash_s *nand_init(int manf_id, int chip_id)
475 474 nand_init_2048(s);
476 475 break;
477 476 default:
478   - cpu_abort(cpu_single_env, "%s: Unsupported NAND block size.\n",
479   - __FUNCTION__);
  477 + hw_error("%s: Unsupported NAND block size.\n", __FUNCTION__);
480 478 }
481 479  
482 480 pagesize = 1 << s->oob_shift;
... ...
hw/nseries.c
  View file @2ac7117
... ... @@ -428,8 +428,7 @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
428 428 uint8_t ret;
429 429  
430 430 if (len > 9)
431   - cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
432   - __FUNCTION__, len);
  431 + hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
433 432  
434 433 if (s->p >= ARRAY_SIZE(s->resp))
435 434 ret = 0;
... ...
hw/omap1.c
  View file @2ac7117
... ... @@ -1531,7 +1531,7 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1531 1531 case omap1510:
1532 1532 return 0x03310115;
1533 1533 default:
1534   - cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
  1534 + hw_error("%s: bad mpu model\n", __FUNCTION__);
1535 1535 }
1536 1536 break;
1537 1537  
... ... @@ -1542,7 +1542,7 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1542 1542 case omap1510:
1543 1543 return 0xfb47002f;
1544 1544 default:
1545   - cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
  1545 + hw_error("%s: bad mpu model\n", __FUNCTION__);
1546 1546 }
1547 1547 break;
1548 1548 }
... ... @@ -2775,15 +2775,14 @@ qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2775 2775 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2776 2776 {
2777 2777 if (line >= 16 || line < 0)
2778   - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
  2778 + hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
2779 2779 s->handler[line] = handler;
2780 2780 }
2781 2781  
2782 2782 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2783 2783 {
2784 2784 if (row >= 5 || row < 0)
2785   - cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
2786   - __FUNCTION__, col, row);
  2785 + hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
2787 2786  
2788 2787 if (down)
2789 2788 s->buttons[row] |= 1 << col;
... ... @@ -2970,7 +2969,7 @@ qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
2970 2969 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
2971 2970 {
2972 2971 if (line >= 16 || line < 0)
2973   - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
  2972 + hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
2974 2973 s->handler[line] = handler;
2975 2974 }
2976 2975  
... ...
hw/omap2.c
  View file @2ac7117
... ... @@ -1070,15 +1070,14 @@ struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
1070 1070 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
1071 1071 {
1072 1072 if (start >= s->modules * 32 || start < 0)
1073   - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
1074   - __FUNCTION__, start);
  1073 + hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
1075 1074 return s->module[start >> 5].in + (start & 31);
1076 1075 }
1077 1076  
1078 1077 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
1079 1078 {
1080 1079 if (line >= s->modules * 32 || line < 0)
1081   - cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
  1080 + hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
1082 1081 s->module[line >> 5].handler[line & 31] = handler;
1083 1082 }
1084 1083  
... ... @@ -1399,8 +1398,7 @@ void omap_mcspi_attach(struct omap_mcspi_s *s,
1399 1398 int chipselect)
1400 1399 {
1401 1400 if (chipselect < 0 || chipselect >= s->chnum)
1402   - cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
1403   - __FUNCTION__, chipselect);
  1401 + hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
1404 1402  
1405 1403 s->ch[chipselect].txrx = txrx;
1406 1404 s->ch[chipselect].opaque = opaque;
... ... @@ -2642,7 +2640,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
2642 2640 case omap3430:
2643 2641 return 0x1b7ae02f; /* ES 2 */
2644 2642 default:
2645   - cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
  2643 + hw_error("%s: Bad mpu model\n", __FUNCTION__);
2646 2644 }
2647 2645  
2648 2646 case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
... ... @@ -2659,7 +2657,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
2659 2657 case omap3430:
2660 2658 return 0x000000f0;
2661 2659 default:
2662   - cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
  2660 + hw_error("%s: Bad mpu model\n", __FUNCTION__);
2663 2661 }
2664 2662  
2665 2663 case 0x20c:
... ... @@ -2673,7 +2671,7 @@ static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
2673 2671 case omap3430:
2674 2672 return 0xcafeb7ae; /* ES 2 */
2675 2673 default:
2676   - cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
  2674 + hw_error("%s: Bad mpu model\n", __FUNCTION__);
2677 2675 }
2678 2676  
2679 2677 case 0x218: /* DIE_ID_reg */
... ...
hw/omap_clk.c
  View file @2ac7117
... ... @@ -1105,7 +1105,7 @@ struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
1105 1105 for (i = mpu->clks; i->name; i ++)
1106 1106 if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
1107 1107 return i;
1108   - cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
  1108 + hw_error("%s: %s not found\n", __FUNCTION__, name);
1109 1109 }
1110 1110  
1111 1111 void omap_clk_get(struct clk *clk)
... ... @@ -1116,8 +1116,7 @@ void omap_clk_get(struct clk *clk)
1116 1116 void omap_clk_put(struct clk *clk)
1117 1117 {
1118 1118 if (!(clk->usecount --))
1119   - cpu_abort(cpu_single_env, "%s: %s is not in use\n",
1120   - __FUNCTION__, clk->name);
  1119 + hw_error("%s: %s is not in use\n", __FUNCTION__, clk->name);
1121 1120 }
1122 1121  
1123 1122 static void omap_clk_update(struct clk *clk)
... ...
hw/omap_dss.c
  View file @2ac7117
... ... @@ -1064,6 +1064,6 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
1064 1064 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip)
1065 1065 {
1066 1066 if (cs < 0 || cs > 1)
1067   - cpu_abort(cpu_single_env, "%s: wrong CS %i\n", __FUNCTION__, cs);
  1067 + hw_error("%s: wrong CS %i\n", __FUNCTION__, cs);
1068 1068 s->rfbi.chip[cs] = chip;
1069 1069 }
... ...
hw/onenand.c
  View file @2ac7117
... ... @@ -156,8 +156,7 @@ static void onenand_reset(struct onenand_s *s, int cold)
156 156 memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
157 157  
158 158 if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0)
159   - cpu_abort(cpu_single_env, "%s: Loading the BootRAM failed.\n",
160   - __FUNCTION__);
  159 + hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
161 160 }
162 161 }
163 162  
... ... @@ -500,7 +499,7 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
500 499 case 0xff02: /* ECC Result of spare area data */
501 500 case 0xff03: /* ECC Result of main area data */
502 501 case 0xff04: /* ECC Result of spare area data */
503   - cpu_abort(cpu_single_env, "%s: imeplement ECC\n", __FUNCTION__);
  502 + hw_error("%s: imeplement ECC\n", __FUNCTION__);
504 503 return 0x0000;
505 504 }
506 505  
... ...
hw/pl011.c
  View file @2ac7117
... ... @@ -103,7 +103,7 @@ static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
103 103 case 18: /* UARTDMACR */
104 104 return s->dmacr;
105 105 default:
106   - cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
  106 + hw_error("pl011_read: Bad offset %x\n", (int)offset);
107 107 return 0;
108 108 }
109 109 }
... ... @@ -175,10 +175,10 @@ static void pl011_write(void *opaque, target_phys_addr_t offset,
175 175 case 18: /* UARTDMACR */
176 176 s->dmacr = value;
177 177 if (value & 3)
178   - cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
  178 + hw_error("PL011: DMA not implemented\n");
179 179 break;
180 180 default:
181   - cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
  181 + hw_error("pl011_write: Bad offset %x\n", (int)offset);
182 182 }
183 183 }
184 184  
... ...
hw/pl022.c
  View file @2ac7117
... ... @@ -168,8 +168,7 @@ static uint32_t pl022_read(void *opaque, target_phys_addr_t offset)
168 168 /* Not implemented. */
169 169 return 0;
170 170 default:
171   - cpu_abort (cpu_single_env, "pl022_read: Bad offset %x\n",
172   - (int)offset);
  171 + hw_error("pl022_read: Bad offset %x\n", (int)offset);
173 172 return 0;
174 173 }
175 174 }
... ... @@ -211,12 +210,12 @@ static void pl022_write(void *opaque, target_phys_addr_t offset,
211 210 pl022_update(s);
212 211 break;
213 212 case 0x20: /* DMACR */
214   - if (value)
215   - cpu_abort (cpu_single_env, "pl022: DMA not implemented\n");
  213 + if (value) {
  214 + hw_error("pl022: DMA not implemented\n");
  215 + }
216 216 break;
217 217 default:
218   - cpu_abort (cpu_single_env, "pl022_write: Bad offset %x\n",
219   - (int)offset);
  218 + hw_error("pl022_write: Bad offset %x\n", (int)offset);
220 219 }
221 220 }
222 221  
... ...
hw/pl031.c
  View file @2ac7117
... ... @@ -119,8 +119,7 @@ static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
119 119 (int)offset);
120 120 break;
121 121 default:
122   - cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
123   - (int)offset);
  122 + hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
124 123 break;
125 124 }
126 125  
... ... @@ -168,8 +167,7 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
168 167 break;
169 168  
170 169 default:
171   - cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
172   - (int)offset);
  170 + hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
173 171 break;
174 172 }
175 173 }
... ... @@ -195,8 +193,9 @@ void pl031_init(uint32_t base, qemu_irq irq)
195 193 s = qemu_mallocz(sizeof(pl031_state));
196 194  
197 195 iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
198   - if (iomemtype == -1)
199   - cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
  196 + if (iomemtype == -1) {
  197 + hw_error("pl031_init: Can't register I/O memory\n");
  198 + }
200 199  
201 200 cpu_register_physical_memory(base, 0x00001000, iomemtype);
202 201  
... ...
hw/pl050.c
  View file @2ac7117
... ... @@ -79,7 +79,7 @@ static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
79 79 case 4: /* KMIIR */
80 80 return s->pending | 2;
81 81 default:
82   - cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", (int)offset);
  82 + hw_error("pl050_read: Bad offset %x\n", (int)offset);
83 83 return 0;
84 84 }
85 85 }
... ... @@ -107,7 +107,7 @@ static void pl050_write(void *opaque, target_phys_addr_t offset,
107 107 s->clk = value;
108 108 return;
109 109 default:
110   - cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", (int)offset);
  110 + hw_error("pl050_write: Bad offset %x\n", (int)offset);
111 111 }
112 112 }
113 113 static CPUReadMemoryFunc *pl050_readfn[] = {
... ...
hw/pl061.c
  View file @2ac7117
... ... @@ -126,8 +126,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
126 126 case 0x524: /* Commit */
127 127 return s->cr;
128 128 default:
129   - cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
130   - (int)offset);
  129 + hw_error("pl061_read: Bad offset %x\n", (int)offset);
131 130 return 0;
132 131 }
133 132 }
... ... @@ -199,8 +198,7 @@ static void pl061_write(void *opaque, target_phys_addr_t offset,
199 198 s->cr = value;
200 199 break;
201 200 default:
202   - cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
203   - (int)offset);
  201 + hw_error("pl061_write: Bad offset %x\n", (int)offset);
204 202 }
205 203 pl061_update(s);
206 204 }
... ...
hw/pl080.c
  View file @2ac7117
... ... @@ -93,7 +93,7 @@ static void pl080_run(pl080_state *s)
93 93 if ((s->conf & PL080_CONF_E) == 0)
94 94 return;
95 95  
96   -cpu_abort(cpu_single_env, "DMA active\n");
  96 +hw_error("DMA active\n");
97 97 /* If we are already in the middle of a DMA operation then indicate that
98 98 there may be new DMA requests and return immediately. */
99 99 if (s->running) {
... ... @@ -111,7 +111,7 @@ again:
111 111 continue;
112 112 flow = (ch->conf >> 11) & 7;
113 113 if (flow >= 4) {
114   - cpu_abort(cpu_single_env,
  114 + hw_error(
115 115 "pl080_run: Peripheral flow control not implemented\n");
116 116 }
117 117 src_id = (ch->conf >> 1) & 0x1f;
... ... @@ -242,7 +242,7 @@ static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
242 242 return s->sync;
243 243 default:
244 244 bad_offset:
245   - cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", (int)offset);
  245 + hw_error("pl080_read: Bad offset %x\n", (int)offset);
246 246 return 0;
247 247 }
248 248 }
... ... @@ -288,13 +288,12 @@ static void pl080_write(void *opaque, target_phys_addr_t offset,
288 288 case 10: /* SoftLBReq */
289 289 case 11: /* SoftLSReq */
290 290 /* ??? Implement these. */
291   - cpu_abort(cpu_single_env, "pl080_write: Soft DMA not implemented\n");
  291 + hw_error("pl080_write: Soft DMA not implemented\n");
292 292 break;
293 293 case 12: /* Configuration */
294 294 s->conf = value;
295 295 if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
296   - cpu_abort(cpu_single_env,
297   - "pl080_write: Big-endian DMA not implemented\n");
  296 + hw_error("pl080_write: Big-endian DMA not implemented\n");
298 297 }
299 298 pl080_run(s);
300 299 break;
... ... @@ -303,7 +302,7 @@ static void pl080_write(void *opaque, target_phys_addr_t offset,
303 302 break;
304 303 default:
305 304 bad_offset:
306   - cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", (int)offset);
  305 + hw_error("pl080_write: Bad offset %x\n", (int)offset);
307 306 }
308 307 pl080_update(s);
309 308 }
... ...
hw/pl110.c
  View file @2ac7117
... ... @@ -267,7 +267,7 @@ static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
267 267 case 12: /* LCDLPCURR */
268 268 return s->lpbase;
269 269 default:
270   - cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
  270 + hw_error("pl110_read: Bad offset %x\n", (int)offset);
271 271 return 0;
272 272 }
273 273 }
... ... @@ -333,7 +333,7 @@ static void pl110_write(void *opaque, target_phys_addr_t offset,
333 333 pl110_update(s);
334 334 break;
335 335 default:
336   - cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
  336 + hw_error("pl110_write: Bad offset %x\n", (int)offset);
337 337 }
338 338 }
339 339  
... ...
hw/pl181.c
  View file @2ac7117
... ... @@ -332,7 +332,7 @@ static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
332 332 return value;
333 333 }
334 334 default:
335   - cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", (int)offset);
  335 + hw_error("pl181_read: Bad offset %x\n", (int)offset);
336 336 return 0;
337 337 }
338 338 }
... ... @@ -403,7 +403,7 @@ static void pl181_write(void *opaque, target_phys_addr_t offset,
403 403 }
404 404 break;
405 405 default:
406   - cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", (int)offset);
  406 + hw_error("pl181_write: Bad offset %x\n", (int)offset);
407 407 }
408 408 pl181_update(s);
409 409 }
... ...
hw/pl190.c
  View file @2ac7117
... ... @@ -137,7 +137,7 @@ static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
137 137 case 13: /* DEFVECTADDR */
138 138 return s->vect_addr[16];
139 139 default:
140   - cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset);
  140 + hw_error("pl190_read: Bad offset %x\n", (int)offset);
141 141 return 0;
142 142 }
143 143 }
... ... @@ -190,11 +190,12 @@ static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
190 190 s->default_addr = val;
191 191 break;
192 192 case 0xc0: /* ITCR */
193   - if (val)
194   - cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
  193 + if (val) {
  194 + hw_error("pl190: Test mode not implemented\n");
  195 + }
195 196 break;
196 197 default:
197   - cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset);
  198 + hw_error("pl190_write: Bad offset %x\n", (int)offset);
198 199 return;
199 200 }
200 201 pl190_update(s);
... ...
hw/ppc_newworld.c
  View file @2ac7117
... ... @@ -146,7 +146,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
146 146 /* Load OpenBIOS (ELF) */
147 147 bios_size = load_elf(buf, 0, NULL, NULL, NULL);
148 148 if (bios_size < 0 || bios_size > BIOS_SIZE) {
149   - cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
  149 + hw_error("qemu: could not load PowerPC bios '%s'\n", buf);
150 150 exit(1);
151 151 }
152 152  
... ... @@ -190,8 +190,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
190 190 kernel_base,
191 191 ram_size - kernel_base);
192 192 if (kernel_size < 0) {
193   - cpu_abort(env, "qemu: could not load kernel '%s'\n",
194   - kernel_filename);
  193 + hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
195 194 exit(1);
196 195 }
197 196 /* load initrd */
... ... @@ -200,8 +199,8 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
200 199 initrd_size = load_image_targphys(initrd_filename, initrd_base,
201 200 ram_size - initrd_base);
202 201 if (initrd_size < 0) {
203   - cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
204   - initrd_filename);
  202 + hw_error("qemu: could not load initial ram disk '%s'\n",
  203 + initrd_filename);
205 204 exit(1);
206 205 }
207 206 } else {
... ... @@ -278,7 +277,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
278 277 break;
279 278 #endif /* defined(TARGET_PPC64) */
280 279 default:
281   - cpu_abort(env, "Bus model not supported on mac99 machine\n");
  280 + hw_error("Bus model not supported on mac99 machine\n");
282 281 exit(1);
283 282 }
284 283 }
... ...
hw/ppc_oldworld.c
  View file @2ac7117
... ... @@ -179,7 +179,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
179 179 /* Load OpenBIOS (ELF) */
180 180 bios_size = load_elf(buf, 0, NULL, NULL, NULL);
181 181 if (bios_size < 0 || bios_size > BIOS_SIZE) {
182   - cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
  182 + hw_error("qemu: could not load PowerPC bios '%s'\n", buf);
183 183 exit(1);
184 184 }
185 185  
... ... @@ -222,7 +222,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
222 222 kernel_base,
223 223 ram_size - kernel_base);
224 224 if (kernel_size < 0) {
225   - cpu_abort(env, "qemu: could not load kernel '%s'\n",
  225 + hw_error("qemu: could not load kernel '%s'\n",
226 226 kernel_filename);
227 227 exit(1);
228 228 }
... ... @@ -232,8 +232,8 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
232 232 initrd_size = load_image_targphys(initrd_filename, initrd_base,
233 233 ram_size - initrd_base);
234 234 if (initrd_size < 0) {
235   - cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
236   - initrd_filename);
  235 + hw_error("qemu: could not load initial ram disk '%s'\n",
  236 + initrd_filename);
237 237 exit(1);
238 238 }
239 239 } else {
... ... @@ -288,15 +288,13 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
288 288 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
289 289 break;
290 290 default:
291   - cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
292   - exit(1);
  291 + hw_error("Bus model not supported on OldWorld Mac machine\n");
293 292 }
294 293 }
295 294  
296 295 /* init basic PC hardware */
297 296 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
298   - cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
299   - exit(1);
  297 + hw_error("Only 6xx bus is supported on heathrow machine\n");
300 298 }
301 299 pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
302 300 pci_bus = pci_grackle_init(0xfec00000, pic);
... ...
hw/ppc_prep.c
  View file @2ac7117
... ... @@ -595,11 +595,10 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
595 595 bios_size = load_image_targphys(buf, bios_addr, bios_size);
596 596 }
597 597 if (bios_size < 0 || bios_size > BIOS_SIZE) {
598   - cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
599   - exit(1);
  598 + hw_error("qemu: could not load PPC PREP bios '%s'\n", buf);
600 599 }
601 600 if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
602   - cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
  601 + hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
603 602 }
604 603  
605 604 if (linux_boot) {
... ... @@ -608,8 +607,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
608 607 kernel_size = load_image_targphys(kernel_filename, kernel_base,
609 608 ram_size - kernel_base);
610 609 if (kernel_size < 0) {
611   - cpu_abort(env, "qemu: could not load kernel '%s'\n",
612   - kernel_filename);
  610 + hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
613 611 exit(1);
614 612 }
615 613 /* load initrd */
... ... @@ -618,9 +616,8 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
618 616 initrd_size = load_image_targphys(initrd_filename, initrd_base,
619 617 ram_size - initrd_base);
620 618 if (initrd_size < 0) {
621   - cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
  619 + hw_error("qemu: could not load initial ram disk '%s'\n",
622 620 initrd_filename);
623   - exit(1);
624 621 }
625 622 } else {
626 623 initrd_base = 0;
... ... @@ -648,8 +645,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
648 645  
649 646 isa_mem_base = 0xc0000000;
650 647 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
651   - cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
652   - exit(1);
  648 + hw_error("Only 6xx bus is supported on PREP machine\n");
653 649 }
654 650 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
655 651 pci_bus = pci_prep_init(i8259);
... ...
hw/pxa2xx_dma.c
  View file @2ac7117
... ... @@ -301,8 +301,7 @@ static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
301 301 }
302 302 }
303 303  
304   - cpu_abort(cpu_single_env,
305   - "%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
  304 + hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
306 305 return 7;
307 306 }
308 307  
... ... @@ -321,8 +320,8 @@ static void pxa2xx_dma_write(void *opaque,
321 320  
322 321 if (value & DRCMR_MAPVLD)
323 322 if ((value & DRCMR_CHLNUM) > s->channels)
324   - cpu_abort(cpu_single_env, "%s: Bad DMA channel %i\n",
325   - __FUNCTION__, value & DRCMR_CHLNUM);
  323 + hw_error("%s: Bad DMA channel %i\n",
  324 + __FUNCTION__, value & DRCMR_CHLNUM);
326 325  
327 326 s->req[channel] = value;
328 327 break;
... ... @@ -401,21 +400,20 @@ static void pxa2xx_dma_write(void *opaque,
401 400 break;
402 401 }
403 402 fail:
404   - cpu_abort(cpu_single_env, "%s: Bad offset " TARGET_FMT_plx "\n",
405   - __FUNCTION__, offset);
  403 + hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
406 404 }
407 405 }
408 406  
409 407 static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset)
410 408 {
411   - cpu_abort(cpu_single_env, "%s: Bad access width\n", __FUNCTION__);
  409 + hw_error("%s: Bad access width\n", __FUNCTION__);
412 410 return 5;
413 411 }
414 412  
415 413 static void pxa2xx_dma_writebad(void *opaque,
416 414 target_phys_addr_t offset, uint32_t value)
417 415 {
418   - cpu_abort(cpu_single_env, "%s: Bad access width\n", __FUNCTION__);
  416 + hw_error("%s: Bad access width\n", __FUNCTION__);
419 417 }
420 418  
421 419 static CPUReadMemoryFunc *pxa2xx_dma_readfn[] = {
... ... @@ -530,8 +528,7 @@ void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on)
530 528 {
531 529 int ch;
532 530 if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
533   - cpu_abort(cpu_single_env,
534   - "%s: Bad DMA request %i\n", __FUNCTION__, req_num);
  531 + hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
535 532  
536 533 if (!(s->req[req_num] & DRCMR_MAPVLD))
537 534 return;
... ...
hw/pxa2xx_gpio.c
  View file @2ac7117
... ... @@ -179,8 +179,7 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
179 179 return s->status[bank];
180 180  
181 181 default:
182   - cpu_abort(cpu_single_env,
183   - "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
  182 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
184 183 }
185 184  
186 185 return 0;
... ... @@ -234,8 +233,7 @@ static void pxa2xx_gpio_write(void *opaque,
234 233 break;
235 234  
236 235 default:
237   - cpu_abort(cpu_single_env,
238   - "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
  236 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
239 237 }
240 238 }
241 239  
... ...
hw/pxa2xx_keypad.c
  View file @2ac7117
... ... @@ -209,8 +209,7 @@ static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset)
209 209 return s->kpkdi;
210 210 break;
211 211 default:
212   - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
213   - __FUNCTION__, offset);
  212 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
214 213 }
215 214  
216 215 return 0;
... ... @@ -254,8 +253,7 @@ static void pxa2xx_keypad_write(void *opaque,
254 253 break;
255 254  
256 255 default:
257   - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
258   - __FUNCTION__, offset);
  256 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
259 257 }
260 258 }
261 259  
... ...
hw/pxa2xx_lcd.c
  View file @2ac7117
... ... @@ -400,8 +400,7 @@ static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
400 400  
401 401 default:
402 402 fail:
403   - cpu_abort(cpu_single_env,
404   - "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
  403 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
405 404 }
406 405  
407 406 return 0;
... ... @@ -556,8 +555,7 @@ static void pxa2xx_lcdc_write(void *opaque,
556 555  
557 556 default:
558 557 fail:
559   - cpu_abort(cpu_single_env,
560   - "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
  558 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
561 559 }
562 560 }
563 561  
... ...
hw/pxa2xx_mmci.c
  View file @2ac7117
... ... @@ -266,8 +266,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
266 266 case MMC_BLKS_REM:
267 267 return s->numblk;
268 268 default:
269   - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
270   - __FUNCTION__, offset);
  269 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
271 270 }
272 271  
273 272 return 0;
... ... @@ -379,8 +378,7 @@ static void pxa2xx_mmci_write(void *opaque,
379 378 break;
380 379  
381 380 default:
382   - cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n",
383   - __FUNCTION__, offset);
  381 + hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
384 382 }
385 383 }
386 384  
... ...
hw/pxa2xx_timer.c
  View file @2ac7117
... ... @@ -205,8 +205,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
205 205 return s->snapshot;
206 206 default:
207 207 badreg:
208   - cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
209   - REG_FMT "\n", offset);
  208 + hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
210 209 }
211 210  
212 211 return 0;
... ... @@ -315,8 +314,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
315 314 break;
316 315 default:
317 316 badreg:
318   - cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
319   - REG_FMT "\n", offset);
  317 + hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
320 318 }
321 319 }
322 320  
... ...
hw/sh_timer.c
  View file @2ac7117
... ... @@ -72,8 +72,7 @@ static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
72 72 if (s->feat & TIMER_FEAT_CAPT)
73 73 return s->tcpr;
74 74 default:
75   - cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
76   - (int)offset);
  75 + hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
77 76 return 0;
78 77 }
79 78 }
... ... @@ -110,23 +109,20 @@ static void sh_timer_write(void *opaque, target_phys_addr_t offset,
110 109 case 4: freq >>= 10; break;
111 110 case 6:
112 111 case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
113   - default: cpu_abort (cpu_single_env,
114   - "sh_timer_write: Reserved TPSC value\n"); break;
  112 + default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
115 113 }
116 114 switch ((value & TIMER_TCR_CKEG) >> 3) {
117 115 case 0: break;
118 116 case 1:
119 117 case 2:
120 118 case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
121   - default: cpu_abort (cpu_single_env,
122   - "sh_timer_write: Reserved CKEG value\n"); break;
  119 + default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
123 120 }
124 121 switch ((value & TIMER_TCR_ICPE) >> 6) {
125 122 case 0: break;
126 123 case 2:
127 124 case 3: if (s->feat & TIMER_FEAT_CAPT) break;
128   - default: cpu_abort (cpu_single_env,
129   - "sh_timer_write: Reserved ICPE value\n"); break;
  125 + default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
130 126 }
131 127 if ((value & TIMER_TCR_UNF) == 0)
132 128 s->int_level = 0;
... ... @@ -134,14 +130,12 @@ static void sh_timer_write(void *opaque, target_phys_addr_t offset,
134 130 value &= ~TIMER_TCR_UNF;
135 131  
136 132 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
137   - cpu_abort (cpu_single_env,
138   - "sh_timer_write: Reserved ICPF value\n");
  133 + hw_error("sh_timer_write: Reserved ICPF value\n");
139 134  
140 135 value &= ~TIMER_TCR_ICPF; /* capture not supported */
141 136  
142 137 if (value & TIMER_TCR_RESERVED)
143   - cpu_abort (cpu_single_env,
144   - "sh_timer_write: Reserved TCR bits set\n");
  138 + hw_error("sh_timer_write: Reserved TCR bits set\n");
145 139 s->tcr = value;
146 140 ptimer_set_limit(s->timer, s->tcor, 0);
147 141 ptimer_set_freq(s->timer, freq);
... ... @@ -156,8 +150,7 @@ static void sh_timer_write(void *opaque, target_phys_addr_t offset,
156 150 break;
157 151 }
158 152 default:
159   - cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
160   - (int)offset);
  153 + hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
161 154 }
162 155 sh_timer_update(s);
163 156 }
... ... @@ -234,8 +227,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
234 227  
235 228 if (offset >= 0x20) {
236 229 if (!(s->feat & TMU012_FEAT_3CHAN))
237   - cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
238   - (int)offset);
  230 + hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
239 231 return sh_timer_read(s->timer[2], offset - 0x20);
240 232 }
241 233  
... ... @@ -251,8 +243,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
251 243 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
252 244 return s->tocr;
253 245  
254   - cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
255   - (int)offset);
  246 + hw_error("tmu012_write: Bad offset %x\n", (int)offset);
256 247 return 0;
257 248 }
258 249  
... ... @@ -267,8 +258,7 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
267 258  
268 259 if (offset >= 0x20) {
269 260 if (!(s->feat & TMU012_FEAT_3CHAN))
270   - cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
271   - (int)offset);
  261 + hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
272 262 sh_timer_write(s->timer[2], offset - 0x20, value);
273 263 return;
274 264 }
... ... @@ -290,7 +280,7 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
290 280 sh_timer_start_stop(s->timer[2], value & (1 << 2));
291 281 else
292 282 if (value & (1 << 2))
293   - cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
  283 + hw_error("tmu012_write: Bad channel\n");
294 284  
295 285 s->tstr = value;
296 286 return;
... ...
hw/smc91c111.c
  View file @2ac7117
... ... @@ -413,8 +413,7 @@ static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
413 413 }
414 414 break;
415 415 }
416   - cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
417   - s->bank, (int)offset);
  416 + hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
418 417 }
419 418  
420 419 static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
... ... @@ -554,8 +553,7 @@ static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
554 553 }
555 554 break;
556 555 }
557   - cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
558   - s->bank, (int)offset);
  556 + hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset);
559 557 return 0;
560 558 }
561 559  
... ...
hw/stellaris.c
  View file @2ac7117
... ... @@ -94,8 +94,7 @@ static void gptm_reload(gptm_state *s, int n, int reset)
94 94 } else if (s->mode[n] == 0xa) {
95 95 /* PWM mode. Not implemented. */
96 96 } else {
97   - cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
98   - s->mode[n]);
  97 + hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
99 98 }
100 99 s->tick[n] = tick;
101 100 qemu_mod_timer(s->timer[n], tick);
... ... @@ -137,8 +136,7 @@ static void gptm_tick(void *opaque)
137 136 } else if (s->mode[n] == 0xa) {
138 137 /* PWM mode. Not implemented. */
139 138 } else {
140   - cpu_abort(cpu_single_env, "TODO: 16-bit timer mode 0x%x\n",
141   - s->mode[n]);
  139 + hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
142 140 }
143 141 gptm_update_irq(s);
144 142 }
... ... @@ -184,9 +182,9 @@ static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
184 182 if (s->control == 1)
185 183 return s->rtc;
186 184 case 0x4c: /* TBR */
187   - cpu_abort(cpu_single_env, "TODO: Timer value read\n");
  185 + hw_error("TODO: Timer value read\n");
188 186 default:
189   - cpu_abort(cpu_single_env, "gptm_read: Bad offset 0x%x\n", (int)offset);
  187 + hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
190 188 return 0;
191 189 }
192 190 }
... ... @@ -266,7 +264,7 @@ static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
266 264 s->match_prescale[0] = value;
267 265 break;
268 266 default:
269   - cpu_abort(cpu_single_env, "gptm_write: Bad offset 0x%x\n", (int)offset);
  267 + hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
270 268 }
271 269 gptm_update_irq(s);
272 270 }
... ... @@ -500,7 +498,7 @@ static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
500 498 case 0x1e4: /* USER1 */
501 499 return s->user1;
502 500 default:
503   - cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);
  501 + hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
504 502 return 0;
505 503 }
506 504 }
... ... @@ -577,7 +575,7 @@ static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
577 575 s->ldoarst = value;
578 576 break;
579 577 default:
580   - cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n", (int)offset);
  578 + hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
581 579 }
582 580 ssys_update(s);
583 581 }
... ... @@ -724,8 +722,7 @@ static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset)
724 722 case 0x20: /* MCR */
725 723 return s->mcr;
726 724 default:
727   - cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x%x\n",
728   - (int)offset);
  725 + hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
729 726 return 0;
730 727 }
731 728 }
... ... @@ -801,15 +798,15 @@ static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
801 798 break;
802 799 case 0x20: /* MCR */
803 800 if (value & 1)
804   - cpu_abort(cpu_single_env,
  801 + hw_error(
805 802 "stellaris_i2c_write: Loopback not implemented\n");
806 803 if (value & 0x20)
807   - cpu_abort(cpu_single_env,
  804 + hw_error(
808 805 "stellaris_i2c_write: Slave mode not implemented\n");
809 806 s->mcr = value & 0x31;
810 807 break;
811 808 default:
812   - cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset 0x%x\n",
  809 + hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
813 810 (int)offset);
814 811 }
815 812 stellaris_i2c_update(s);
... ... @@ -1036,7 +1033,7 @@ static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset)
1036 1033 case 0x30: /* SAC */
1037 1034 return s->sac;
1038 1035 default:
1039   - cpu_abort(cpu_single_env, "strllaris_adc_read: Bad offset 0x%x\n",
  1036 + hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1040 1037 (int)offset);
1041 1038 return 0;
1042 1039 }
... ... @@ -1057,7 +1054,7 @@ static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
1057 1054 return;
1058 1055 case 0x04: /* SSCTL */
1059 1056 if (value != 6) {
1060   - cpu_abort(cpu_single_env, "ADC: Unimplemented sequence %x\n",
  1057 + hw_error("ADC: Unimplemented sequence %x\n",
1061 1058 value);
1062 1059 }
1063 1060 s->ssctl[n] = value;
... ... @@ -1070,8 +1067,7 @@ static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
1070 1067 case 0x00: /* ACTSS */
1071 1068 s->actss = value & 0xf;
1072 1069 if (value & 0xe) {
1073   - cpu_abort(cpu_single_env,
1074   - "Not implemented: ADC sequencers 1-3\n");
  1070 + hw_error("Not implemented: ADC sequencers 1-3\n");
1075 1071 }
1076 1072 break;
1077 1073 case 0x08: /* IM */
... ... @@ -1093,14 +1089,13 @@ static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
1093 1089 s->sspri = value;
1094 1090 break;
1095 1091 case 0x28: /* PSSI */
1096   - cpu_abort(cpu_single_env, "Not implemented: ADC sample initiate\n");
  1092 + hw_error("Not implemented: ADC sample initiate\n");
1097 1093 break;
1098 1094 case 0x30: /* SAC */
1099 1095 s->sac = value;
1100 1096 break;
1101 1097 default:
1102   - cpu_abort(cpu_single_env, "stellaris_adc_write: Bad offset 0x%x\n",
1103   - (int)offset);
  1098 + hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1104 1099 }
1105 1100 stellaris_adc_update(s);
1106 1101 }
... ...
hw/stellaris_enet.c
  View file @2ac7117
... ... @@ -190,8 +190,7 @@ static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
190 190 case 0x3c: /* Undocuented: Timestamp? */
191 191 return 0;
192 192 default:
193   - cpu_abort (cpu_single_env, "stellaris_enet_read: Bad offset %x\n",
194   - (int)offset);
  193 + hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
195 194 return 0;
196 195 }
197 196 }
... ... @@ -298,8 +297,7 @@ static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
298 297 /* Ignored. */
299 298 break;
300 299 default:
301   - cpu_abort (cpu_single_env, "stellaris_enet_write: Bad offset %x\n",
302   - (int)offset);
  300 + hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
303 301 }
304 302 }
305 303  
... ...
hw/tsc210x.c
  View file @2ac7117
... ... @@ -893,7 +893,7 @@ static uint16_t tsc210x_read(struct tsc210x_state_s *s)
893 893 ret = tsc2102_audio_register_read(s, s->offset);
894 894 break;
895 895 default:
896   - cpu_abort(cpu_single_env, "tsc210x_read: wrong memory page\n");
  896 + hw_error("tsc210x_read: wrong memory page\n");
897 897 }
898 898  
899 899 tsc210x_pin_update(s);
... ... @@ -930,8 +930,7 @@ static void tsc210x_write(struct tsc210x_state_s *s, uint16_t value)
930 930 tsc2102_audio_register_write(s, s->offset, value);
931 931 break;
932 932 default:
933   - cpu_abort(cpu_single_env,
934   - "tsc210x_write: wrong memory page\n");
  933 + hw_error("tsc210x_write: wrong memory page\n");
935 934 }
936 935  
937 936 tsc210x_pin_update(s);
... ... @@ -945,8 +944,7 @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
945 944 uint32_t ret = 0;
946 945  
947 946 if (len != 16)
948   - cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
949   - __FUNCTION__, len);
  947 + hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
950 948  
951 949 /* TODO: sequential reads etc - how do we make sure the host doesn't
952 950 * unintentionally read out a conversion result from a register while
... ...
hw/tusb6010.c
  View file @2ac7117
... ... @@ -513,8 +513,7 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
513 513 s->dev_config = value;
514 514 s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
515 515 if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
516   - cpu_abort(cpu_single_env, "%s: Product Test mode not allowed\n",
517   - __FUNCTION__);
  516 + hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
518 517 break;
519 518  
520 519 case TUSB_PHY_OTG_CTRL_ENABLE:
... ...
hw/usb-musb.c
  View file @2ac7117
... ... @@ -556,7 +556,7 @@ static int musb_timeout(int ttype, int speed, int val)
556 556 /* TODO: what with low-speed Bulk and Isochronous? */
557 557 }
558 558  
559   - cpu_abort(cpu_single_env, "bad interval\n");
  559 + hw_error("bad interval\n");
560 560 }
561 561  
562 562 static inline void musb_packet(struct musb_s *s, struct musb_ep_s *ep,
... ...