gwj / at91sam9263 · Commits

Commit 2abec30bcf132b4f9e5911c4155e2a32a33665e9

Authored by ths
1 parent 509b8ab2

Memory-mapped interface for VGA, by Herve Poussineau. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2740 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 109 additions and 1 deletions
hw/mips_pica61.c
  View file @2abec30
... ... @@ -166,7 +166,10 @@ void mips_pica61_init (int ram_size, int vga_ram_size, int boot_device,
166 166 ds1225y_init(0x80009000, "nvram");
167 167  
168 168 /* Video card */
169   - //isa_vga_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
  169 + /* FIXME: This card is not the real one which was in the original PICA,
  170 + * but let's do with what Qemu currenly emulates... */
  171 + isa_vga_mm_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size,
  172 + 0x40000000, 0x60000000, 0);
170 173 }
171 174  
172 175 QEMUMachine mips_pica61_machine = {
... ...
hw/vga.c
  View file @2abec30
... ... @@ -1845,6 +1845,81 @@ void vga_init(VGAState *s)
1845 1845 vga_io_memory);
1846 1846 }
1847 1847  
  1848 +/* Memory mapped interface */
  1849 +static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
  1850 +{
  1851 + VGAState *s = opaque;
  1852 +
  1853 + return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xff;
  1854 +}
  1855 +
  1856 +static void vga_mm_writeb (void *opaque,
  1857 + target_phys_addr_t addr, uint32_t value)
  1858 +{
  1859 + VGAState *s = opaque;
  1860 +
  1861 + vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xff);
  1862 +}
  1863 +
  1864 +static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
  1865 +{
  1866 + VGAState *s = opaque;
  1867 +
  1868 + return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xffff;
  1869 +}
  1870 +
  1871 +static void vga_mm_writew (void *opaque,
  1872 + target_phys_addr_t addr, uint32_t value)
  1873 +{
  1874 + VGAState *s = opaque;
  1875 +
  1876 + vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xffff);
  1877 +}
  1878 +
  1879 +static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
  1880 +{
  1881 + VGAState *s = opaque;
  1882 +
  1883 + return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift);
  1884 +}
  1885 +
  1886 +static void vga_mm_writel (void *opaque,
  1887 + target_phys_addr_t addr, uint32_t value)
  1888 +{
  1889 + VGAState *s = opaque;
  1890 +
  1891 + vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value);
  1892 +}
  1893 +
  1894 +static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
  1895 + &vga_mm_readb,
  1896 + &vga_mm_readw,
  1897 + &vga_mm_readl,
  1898 +};
  1899 +
  1900 +static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
  1901 + &vga_mm_writeb,
  1902 + &vga_mm_writew,
  1903 + &vga_mm_writel,
  1904 +};
  1905 +
  1906 +static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
  1907 + target_phys_addr_t ctrl_base, int it_shift)
  1908 +{
  1909 + int s_ioport_ctrl, vga_io_memory;
  1910 +
  1911 + s->base_ctrl = ctrl_base;
  1912 + s->it_shift = it_shift;
  1913 + s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
  1914 + vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
  1915 +
  1916 + register_savevm("vga", 0, 2, vga_save, vga_load, s);
  1917 +
  1918 + cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
  1919 + s->bank_offset = 0;
  1920 + cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
  1921 +}
  1922 +
1848 1923 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1849 1924 unsigned long vga_ram_offset, int vga_ram_size)
1850 1925 {
... ... @@ -1867,6 +1942,30 @@ int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1867 1942 return 0;
1868 1943 }
1869 1944  
  1945 +int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
  1946 + unsigned long vga_ram_offset, int vga_ram_size,
  1947 + target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
  1948 + int it_shift)
  1949 +{
  1950 + VGAState *s;
  1951 +
  1952 + s = qemu_mallocz(sizeof(VGAState));
  1953 + if (!s)
  1954 + return -1;
  1955 +
  1956 + vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
  1957 + vga_mm_init(s, vram_base, ctrl_base, it_shift);
  1958 +
  1959 + graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);
  1960 +
  1961 +#ifdef CONFIG_BOCHS_VBE
  1962 + /* XXX: use optimized standard vga accesses */
  1963 + cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
  1964 + vga_ram_size, vga_ram_offset);
  1965 +#endif
  1966 + return 0;
  1967 +}
  1968 +
1870 1969 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1871 1970 unsigned long vga_ram_offset, int vga_ram_size,
1872 1971 unsigned long vga_bios_offset, int vga_bios_size)
... ...
hw/vga_int.h
  View file @2abec30
... ... @@ -85,6 +85,8 @@
85 85 unsigned int vram_size; \
86 86 unsigned long bios_offset; \
87 87 unsigned int bios_size; \
  88 + target_phys_addr_t base_ctrl; \
  89 + int it_shift; \
88 90 PCIDevice *pci_dev; \
89 91 uint32_t latch; \
90 92 uint8_t sr_index; \
... ...
... ... @@ -931,6 +931,10 @@ int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
931 931 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
932 932 unsigned long vga_ram_offset, int vga_ram_size,
933 933 unsigned long vga_bios_offset, int vga_bios_size);
  934 +int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
  935 + unsigned long vga_ram_offset, int vga_ram_size,
  936 + target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
  937 + int it_shift);
934 938  
935 939 /* cirrus_vga.c */
936 940 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
... ...