gwj / at91sam9263 · Commits

Commit 2a9859e7246557944f7c008ddf05fc1d2fbc7938

Authored by Edgar E. Iglesias
1 parent 4b816985

ETRAX-SER: Untabify. 

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Inline Side-by-side
Showing 1 changed file with 93 additions and 93 deletions
hw/etraxfs_ser.c
  View file @2a9859e
@@ -45,115 +45,115 @@ @@ -45,115 +45,115 @@
45 45
46 struct etrax_serial 46 struct etrax_serial
47 { 47 {
48 - SysBusDevice busdev;  
49 - CharDriverState *chr;  
50 - qemu_irq irq; 48 + SysBusDevice busdev;
  49 + CharDriverState *chr;
  50 + qemu_irq irq;
51 51
52 - /* This pending thing is a hack. */  
53 - int pending_tx; 52 + /* This pending thing is a hack. */
  53 + int pending_tx;
54 54
55 - /* Control registers. */  
56 - uint32_t regs[R_MAX]; 55 + /* Control registers. */
  56 + uint32_t regs[R_MAX];
57 }; 57 };
58 58
59 static void ser_update_irq(struct etrax_serial *s) 59 static void ser_update_irq(struct etrax_serial *s)
60 { 60 {
61 - s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]);  
62 - s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK]; 61 + s->regs[R_INTR] &= ~(s->regs[RW_ACK_INTR]);
  62 + s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
63 63
64 - qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);  
65 - s->regs[RW_ACK_INTR] = 0; 64 + qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
  65 + s->regs[RW_ACK_INTR] = 0;
66 } 66 }
67 67
68 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr) 68 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
69 { 69 {
70 - struct etrax_serial *s = opaque;  
71 - D(CPUState *env = s->env);  
72 - uint32_t r = 0;  
73 -  
74 - addr >>= 2;  
75 - switch (addr)  
76 - {  
77 - case R_STAT_DIN:  
78 - r = s->regs[RS_STAT_DIN];  
79 - break;  
80 - case RS_STAT_DIN:  
81 - r = s->regs[addr];  
82 - /* Read side-effect: clear dav. */  
83 - s->regs[addr] &= ~(1 << STAT_DAV);  
84 - break;  
85 - default:  
86 - r = s->regs[addr];  
87 - D(printf ("%s %x=%x\n", __func__, addr, r));  
88 - break;  
89 - }  
90 - return r; 70 + struct etrax_serial *s = opaque;
  71 + D(CPUState *env = s->env);
  72 + uint32_t r = 0;
  73 +
  74 + addr >>= 2;
  75 + switch (addr)
  76 + {
  77 + case R_STAT_DIN:
  78 + r = s->regs[RS_STAT_DIN];
  79 + break;
  80 + case RS_STAT_DIN:
  81 + r = s->regs[addr];
  82 + /* Read side-effect: clear dav. */
  83 + s->regs[addr] &= ~(1 << STAT_DAV);
  84 + break;
  85 + default:
  86 + r = s->regs[addr];
  87 + D(printf ("%s %x=%x\n", __func__, addr, r));
  88 + break;
  89 + }
  90 + return r;
91 } 91 }
92 92
93 static void 93 static void
94 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value) 94 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
95 { 95 {
96 - struct etrax_serial *s = opaque;  
97 - unsigned char ch = value;  
98 - D(CPUState *env = s->env);  
99 -  
100 - D(printf ("%s %x %x\n", __func__, addr, value));  
101 - addr >>= 2;  
102 - switch (addr)  
103 - {  
104 - case RW_DOUT:  
105 - qemu_chr_write(s->chr, &ch, 1);  
106 - s->regs[R_INTR] |= 1;  
107 - s->pending_tx = 1;  
108 - s->regs[addr] = value;  
109 - break;  
110 - case RW_ACK_INTR:  
111 - s->regs[addr] = value;  
112 - if (s->pending_tx && (s->regs[addr] & 1)) {  
113 - s->regs[R_INTR] |= 1;  
114 - s->pending_tx = 0;  
115 - s->regs[addr] &= ~1;  
116 - }  
117 - break;  
118 - default:  
119 - s->regs[addr] = value;  
120 - break;  
121 - }  
122 - ser_update_irq(s); 96 + struct etrax_serial *s = opaque;
  97 + unsigned char ch = value;
  98 + D(CPUState *env = s->env);
  99 +
  100 + D(printf ("%s %x %x\n", __func__, addr, value));
  101 + addr >>= 2;
  102 + switch (addr)
  103 + {
  104 + case RW_DOUT:
  105 + qemu_chr_write(s->chr, &ch, 1);
  106 + s->regs[R_INTR] |= 1;
  107 + s->pending_tx = 1;
  108 + s->regs[addr] = value;
  109 + break;
  110 + case RW_ACK_INTR:
  111 + s->regs[addr] = value;
  112 + if (s->pending_tx && (s->regs[addr] & 1)) {
  113 + s->regs[R_INTR] |= 1;
  114 + s->pending_tx = 0;
  115 + s->regs[addr] &= ~1;
  116 + }
  117 + break;
  118 + default:
  119 + s->regs[addr] = value;
  120 + break;
  121 + }
  122 + ser_update_irq(s);
123 } 123 }
124 124
125 static CPUReadMemoryFunc *ser_read[] = { 125 static CPUReadMemoryFunc *ser_read[] = {
126 - NULL, NULL,  
127 - &ser_readl, 126 + NULL, NULL,
  127 + &ser_readl,
128 }; 128 };
129 129
130 static CPUWriteMemoryFunc *ser_write[] = { 130 static CPUWriteMemoryFunc *ser_write[] = {
131 - NULL, NULL,  
132 - &ser_writel, 131 + NULL, NULL,
  132 + &ser_writel,
133 }; 133 };
134 134
135 static void serial_receive(void *opaque, const uint8_t *buf, int size) 135 static void serial_receive(void *opaque, const uint8_t *buf, int size)
136 { 136 {
137 - struct etrax_serial *s = opaque; 137 + struct etrax_serial *s = opaque;
138 138
139 - s->regs[R_INTR] |= 8;  
140 - s->regs[RS_STAT_DIN] &= ~0xff;  
141 - s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);  
142 - s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */  
143 - ser_update_irq(s); 139 + s->regs[R_INTR] |= 8;
  140 + s->regs[RS_STAT_DIN] &= ~0xff;
  141 + s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
  142 + s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */
  143 + ser_update_irq(s);
144 } 144 }
145 145
146 static int serial_can_receive(void *opaque) 146 static int serial_can_receive(void *opaque)
147 { 147 {
148 - struct etrax_serial *s = opaque;  
149 - int r; 148 + struct etrax_serial *s = opaque;
  149 + int r;
150 150
151 - /* Is the receiver enabled? */  
152 - r = s->regs[RW_REC_CTRL] & 1; 151 + /* Is the receiver enabled? */
  152 + r = s->regs[RW_REC_CTRL] & 1;
153 153
154 - /* Pending rx data? */  
155 - r |= !(s->regs[R_INTR] & 8);  
156 - return r; 154 + /* Pending rx data? */
  155 + r |= !(s->regs[R_INTR] & 8);
  156 + return r;
157 } 157 }
158 158
159 static void serial_event(void *opaque, int event) 159 static void serial_event(void *opaque, int event)
@@ -163,27 +163,27 @@ static void serial_event(void *opaque, int event) @@ -163,27 +163,27 @@ static void serial_event(void *opaque, int event)
163 163
164 static void etraxfs_ser_init(SysBusDevice *dev) 164 static void etraxfs_ser_init(SysBusDevice *dev)
165 { 165 {
166 - struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);  
167 - int ser_regs;  
168 -  
169 - /* transmitter begins ready and idle. */  
170 - s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);  
171 - s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);  
172 -  
173 - sysbus_init_irq(dev, &s->irq);  
174 - ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);  
175 - sysbus_init_mmio(dev, R_MAX * 4, ser_regs);  
176 - s->chr = qdev_init_chardev(&dev->qdev);  
177 - if (s->chr)  
178 - qemu_chr_add_handlers(s->chr,  
179 - serial_can_receive, serial_receive,  
180 - serial_event, s); 166 + struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
  167 + int ser_regs;
  168 +
  169 + /* transmitter begins ready and idle. */
  170 + s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
  171 + s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
  172 +
  173 + sysbus_init_irq(dev, &s->irq);
  174 + ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
  175 + sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
  176 + s->chr = qdev_init_chardev(&dev->qdev);
  177 + if (s->chr)
  178 + qemu_chr_add_handlers(s->chr,
  179 + serial_can_receive, serial_receive,
  180 + serial_event, s);
181 } 181 }
182 182
183 static void etraxfs_serial_register(void) 183 static void etraxfs_serial_register(void)
184 { 184 {
185 - sysbus_register_dev("etraxfs,serial", sizeof (struct etrax_serial),  
186 - etraxfs_ser_init); 185 + sysbus_register_dev("etraxfs,serial", sizeof (struct etrax_serial),
  186 + etraxfs_ser_init);
187 } 187 }
188 188
189 device_init(etraxfs_serial_register) 189 device_init(etraxfs_serial_register)