Commit 2a449d14922cdd65ba4bf566ad114e37e61c89e1

Authored by bellard
1 parent 90426a4e

fixed x86_64 regression

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4586 c046a42c-6fe2-441c-8c8c-71466251a162
Showing 1 changed file with 4 additions and 4 deletions
target-i386/translate.c
... ... @@ -1511,15 +1511,15 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1511 1511 if (is_right) {
1512 1512 if (is_arith) {
1513 1513 gen_exts(ot, cpu_T[0]);
1514   - tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], op2 - 1);
  1514 + tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1515 1515 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1516 1516 } else {
1517 1517 gen_extu(ot, cpu_T[0]);
1518   - tcg_gen_shri_tl(cpu_tmp0, cpu_T[0], op2 - 1);
  1518 + tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1519 1519 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1520 1520 }
1521 1521 } else {
1522   - tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], op2 - 1);
  1522 + tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1523 1523 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1524 1524 }
1525 1525 }
... ... @@ -1532,7 +1532,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1532 1532  
1533 1533 /* update eflags if non zero shift */
1534 1534 if (op2 != 0) {
1535   - tcg_gen_mov_tl(cpu_cc_src, cpu_tmp0);
  1535 + tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1536 1536 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1537 1537 if (is_right)
1538 1538 s->cc_op = CC_OP_SARB + ot;
... ...