gwj / at91sam9263 · Commits

Commit 29fe0e3490ef63f564f426fc526d4415f44e7052

Authored by ths
1 parent 3aa662fa

5K and 20K are Release 1 CPUs. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3858 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 3 additions and 3 deletions
target-mips/translate_init.c
  View file @29fe0e3
@@ -308,7 +308,7 @@ static mips_def_t mips_defs[] = @@ -308,7 +308,7 @@ static mips_def_t mips_defs[] =
308 { 308 {
309 .name = "5Kc", 309 .name = "5Kc",
310 .CP0_PRid = 0x00018100, 310 .CP0_PRid = 0x00018100,
311 - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 311 + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
312 (MMU_TYPE_R4000 << CP0C0_MT), 312 (MMU_TYPE_R4000 << CP0C0_MT),
313 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | 313 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
314 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 314 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
@@ -327,7 +327,7 @@ static mips_def_t mips_defs[] = @@ -327,7 +327,7 @@ static mips_def_t mips_defs[] =
327 { 327 {
328 .name = "5Kf", 328 .name = "5Kf",
329 .CP0_PRid = 0x00018100, 329 .CP0_PRid = 0x00018100,
330 - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 330 + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
331 (MMU_TYPE_R4000 << CP0C0_MT), 331 (MMU_TYPE_R4000 << CP0C0_MT),
332 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | 332 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
333 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 333 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
@@ -351,7 +351,7 @@ static mips_def_t mips_defs[] = @@ -351,7 +351,7 @@ static mips_def_t mips_defs[] =
351 /* We emulate a later version of the 20Kc, earlier ones had a broken 351 /* We emulate a later version of the 20Kc, earlier ones had a broken
352 WAIT instruction. */ 352 WAIT instruction. */
353 .CP0_PRid = 0x000182a0, 353 .CP0_PRid = 0x000182a0,
354 - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 354 + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
355 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), 355 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
356 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | 356 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
357 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 357 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |