gwj / at91sam9263 · Commits

Commit 29cf4b75160f9d518fc43df1463fd86b35f4cfda

Authored by ths
1 parent b6ce8f0a

Remove the temporaries cache of the MIPS target. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4666 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 46 additions and 83 deletions
target-mips/translate.c
  View file @29cf4b7
... ... @@ -425,46 +425,6 @@ enum {
425 425 /* global register indices */
426 426 static TCGv cpu_env, current_tc_gprs, current_tc_hi, cpu_T[2];
427 427  
428   -/* The code generator doesn't like lots of temporaries, so maintain our own
429   - cache for reuse within a function. */
430   -#define MAX_TEMPS 4
431   -static int num_temps;
432   -static TCGv temps[MAX_TEMPS];
433   -
434   -/* Allocate a temporary variable. */
435   -static TCGv new_tmp(void)
436   -{
437   - TCGv tmp;
438   - if (num_temps == MAX_TEMPS)
439   - abort();
440   -
441   - if (GET_TCGV(temps[num_temps]))
442   - return temps[num_temps++];
443   -
444   - tmp = tcg_temp_new(TCG_TYPE_I32);
445   - temps[num_temps++] = tmp;
446   - return tmp;
447   -}
448   -
449   -/* Release a temporary variable. */
450   -static void dead_tmp(TCGv tmp)
451   -{
452   - int i;
453   - num_temps--;
454   - i = num_temps;
455   - if (GET_TCGV(temps[i]) == GET_TCGV(tmp))
456   - return;
457   -
458   - /* Shuffle this temp to the last slot. */
459   - while (GET_TCGV(temps[i]) != GET_TCGV(tmp))
460   - i--;
461   - while (i < num_temps) {
462   - temps[i] = temps[i + 1];
463   - i++;
464   - }
465   - temps[i] = tmp;
466   -}
467   -
468 428 typedef struct DisasContext {
469 429 struct TranslationBlock *tb;
470 430 target_ulong pc, saved_pc;
... ... @@ -564,7 +524,7 @@ static inline void gen_load_srsgpr (TCGv t, int reg)
564 524 if (reg == 0)
565 525 tcg_gen_movi_tl(t, 0);
566 526 else {
567   - TCGv r_tmp = new_tmp();
  527 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
568 528  
569 529 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
570 530 tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
... ... @@ -573,14 +533,14 @@ static inline void gen_load_srsgpr (TCGv t, int reg)
573 533 tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
574 534  
575 535 tcg_gen_ld_tl(t, r_tmp, sizeof(target_ulong) * reg);
576   - dead_tmp(r_tmp);
  536 + tcg_temp_free(r_tmp);
577 537 }
578 538 }
579 539  
580 540 static inline void gen_store_srsgpr (TCGv t, int reg)
581 541 {
582 542 if (reg != 0) {
583   - TCGv r_tmp = new_tmp();
  543 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
584 544  
585 545 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
586 546 tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
... ... @@ -589,7 +549,7 @@ static inline void gen_store_srsgpr (TCGv t, int reg)
589 549 tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
590 550  
591 551 tcg_gen_st_tl(t, r_tmp, sizeof(target_ulong) * reg);
592   - dead_tmp(r_tmp);
  552 + tcg_temp_free(r_tmp);
593 553 }
594 554 }
595 555  
... ... @@ -739,7 +699,7 @@ OP_CONDZ(ltz, TCG_COND_LT);
739 699 static inline void gen_save_pc(target_ulong pc)
740 700 {
741 701 TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
742   - TCGv r_tc_off = new_tmp();
  702 + TCGv r_tc_off = tcg_temp_new(TCG_TYPE_I32);
743 703 TCGv r_tc_off_ptr = tcg_temp_new(TCG_TYPE_PTR);
744 704 TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
745 705  
... ... @@ -749,13 +709,16 @@ static inline void gen_save_pc(target_ulong pc)
749 709 tcg_gen_ext_i32_ptr(r_tc_off_ptr, r_tc_off);
750 710 tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
751 711 tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
752   - dead_tmp(r_tc_off);
  712 + tcg_temp_free(r_tc_off);
  713 + tcg_temp_free(r_tc_off_tl);
  714 + tcg_temp_free(r_ptr);
  715 + tcg_temp_free(r_tmp);
753 716 }
754 717  
755 718 static inline void gen_breg_pc(void)
756 719 {
757 720 TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
758   - TCGv r_tc_off = new_tmp();
  721 + TCGv r_tc_off = tcg_temp_new(TCG_TYPE_I32);
759 722 TCGv r_tc_off_ptr = tcg_temp_new(TCG_TYPE_PTR);
760 723 TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
761 724  
... ... @@ -765,7 +728,10 @@ static inline void gen_breg_pc(void)
765 728 tcg_gen_ext_i32_ptr(r_tc_off_ptr, r_tc_off);
766 729 tcg_gen_add_ptr(r_ptr, cpu_env, r_tc_off_ptr);
767 730 tcg_gen_st_tl(r_tmp, r_ptr, offsetof(CPUState, PC));
768   - dead_tmp(r_tc_off);
  731 + tcg_temp_free(r_tc_off);
  732 + tcg_temp_free(r_tc_off_tl);
  733 + tcg_temp_free(r_ptr);
  734 + tcg_temp_free(r_tmp);
769 735 }
770 736  
771 737 static inline void gen_save_btarget(target_ulong btarget)
... ... @@ -853,18 +819,24 @@ static inline void gen_op_addr_add (void)
853 819 with Status_UX = 0 should be casted to 32-bit and sign extended.
854 820 See the MIPS64 PRA manual, section 4.10. */
855 821 {
856   - TCGv r_tmp = new_tmp();
857 822 int l1 = gen_new_label();
858 823  
859   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
860   - tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
861   - tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
862   - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
863   - tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
864   - tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
  824 + {
  825 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
  826 +
  827 + tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
  828 + tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
  829 + tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
  830 + }
  831 + {
  832 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
  833 +
  834 + tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
  835 + tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
  836 + tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
  837 + }
865 838 tcg_gen_ext32s_i64(cpu_T[0], cpu_T[0]);
866 839 gen_set_label(l1);
867   - dead_tmp(r_tmp);
868 840 }
869 841 #endif
870 842 }
... ... @@ -1413,8 +1385,8 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1413 1385 /* rotr is decoded as srl on non-R2 CPUs */
1414 1386 if (env->insn_flags & ISA_MIPS32R2) {
1415 1387 if (uimm != 0) {
1416   - TCGv r_tmp1 = new_tmp();
1417   - TCGv r_tmp2 = new_tmp();
  1388 + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
  1389 + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
1418 1390  
1419 1391 tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
1420 1392 tcg_gen_movi_i32(r_tmp2, 0x20);
... ... @@ -1423,8 +1395,8 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1423 1395 tcg_gen_shri_i32(r_tmp1, r_tmp1, uimm);
1424 1396 tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp2);
1425 1397 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
1426   - dead_tmp(r_tmp1);
1427   - dead_tmp(r_tmp2);
  1398 + tcg_temp_free(r_tmp1);
  1399 + tcg_temp_free(r_tmp2);
1428 1400 }
1429 1401 opn = "rotr";
1430 1402 } else {
... ... @@ -1751,9 +1723,9 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1751 1723 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x1f);
1752 1724 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
1753 1725 {
1754   - TCGv r_tmp1 = new_tmp();
1755   - TCGv r_tmp2 = new_tmp();
1756   - TCGv r_tmp3 = new_tmp();
  1726 + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
  1727 + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
  1728 + TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
1757 1729  
1758 1730 tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
1759 1731 tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
... ... @@ -1763,9 +1735,9 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1763 1735 tcg_gen_shr_i32(r_tmp1, r_tmp2, r_tmp1);
1764 1736 tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp3);
1765 1737 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp1);
1766   - dead_tmp(r_tmp1);
1767   - dead_tmp(r_tmp2);
1768   - dead_tmp(r_tmp3);
  1738 + tcg_temp_free(r_tmp1);
  1739 + tcg_temp_free(r_tmp2);
  1740 + tcg_temp_free(r_tmp3);
1769 1741 tcg_gen_br(l2);
1770 1742 }
1771 1743 gen_set_label(l1);
... ... @@ -1930,9 +1902,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1930 1902 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
1931 1903 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
1932 1904 {
1933   - TCGv r_tmp1 = new_tmp();
1934   - TCGv r_tmp2 = new_tmp();
1935   - TCGv r_tmp3 = new_tmp();
  1905 + TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
  1906 + TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
  1907 + TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
1936 1908  
1937 1909 tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
1938 1910 tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
... ... @@ -1940,11 +1912,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1940 1912 tcg_gen_remu_i32(r_tmp1, r_tmp1, r_tmp2);
1941 1913 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp3);
1942 1914 tcg_gen_ext_i32_tl(cpu_T[1], r_tmp1);
  1915 + tcg_temp_free(r_tmp1);
  1916 + tcg_temp_free(r_tmp2);
  1917 + tcg_temp_free(r_tmp3);
1943 1918 gen_store_LO(cpu_T[0], 0);
1944 1919 gen_store_HI(cpu_T[1], 0);
1945   - dead_tmp(r_tmp1);
1946   - dead_tmp(r_tmp2);
1947   - dead_tmp(r_tmp3);
1948 1920 }
1949 1921 gen_set_label(l1);
1950 1922 }
... ... @@ -5566,13 +5538,13 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5566 5538 gen_load_gpr(cpu_T[1], rs);
5567 5539 {
5568 5540 TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
5569   - TCGv r_tmp = new_tmp();
  5541 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
5570 5542  
5571 5543 tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
5572 5544 tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
  5545 + tcg_temp_free(r_ptr);
5573 5546 tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
5574 5547 tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
5575   - dead_tmp(r_tmp);
5576 5548 }
5577 5549 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
5578 5550  
... ... @@ -7251,9 +7223,6 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7251 7223 if (search_pc && loglevel)
7252 7224 fprintf (logfile, "search pc %d\n", search_pc);
7253 7225  
7254   - num_temps = 0;
7255   - memset(temps, 0, sizeof(temps));
7256   -
7257 7226 pc_start = tb->pc;
7258 7227 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7259 7228 ctx.pc = pc_start;
... ... @@ -7308,12 +7277,6 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
7308 7277 }
7309 7278 ctx.opcode = ldl_code(ctx.pc);
7310 7279 decode_opc(env, &ctx);
7311   - if (num_temps) {
7312   - fprintf(stderr,
7313   - "Internal resource leak before " TARGET_FMT_lx "\n",
7314   - ctx.pc);
7315   - num_temps = 0;
7316   - }
7317 7280 ctx.pc += 4;
7318 7281  
7319 7282 if (env->singlestep_enabled)
... ...