Commit 2796188e563dcb2c1e8d75e02ca284bb9dc792e3
1 parent
b5dc7732
Avoid unused input arguments which triggered tcg errors. Spotted by
Stefan Weil. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4795 c046a42c-6fe2-441c-8c8c-71466251a162
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3 changed files
with
30 additions
and
28 deletions
target-mips/helper.h
| @@ -239,14 +239,14 @@ FOP_PROTO(ngt) | @@ -239,14 +239,14 @@ FOP_PROTO(ngt) | ||
| 239 | #undef FOP_PROTO | 239 | #undef FOP_PROTO |
| 240 | 240 | ||
| 241 | /* Special functions */ | 241 | /* Special functions */ |
| 242 | -DEF_HELPER(target_ulong, do_di, (target_ulong t0)) | ||
| 243 | -DEF_HELPER(target_ulong, do_ei, (target_ulong t0)) | 242 | +DEF_HELPER(target_ulong, do_di, (void)) |
| 243 | +DEF_HELPER(target_ulong, do_ei, (void)) | ||
| 244 | DEF_HELPER(void, do_eret, (void)) | 244 | DEF_HELPER(void, do_eret, (void)) |
| 245 | DEF_HELPER(void, do_deret, (void)) | 245 | DEF_HELPER(void, do_deret, (void)) |
| 246 | -DEF_HELPER(target_ulong, do_rdhwr_cpunum, (target_ulong t0)) | ||
| 247 | -DEF_HELPER(target_ulong, do_rdhwr_synci_step, (target_ulong t0)) | ||
| 248 | -DEF_HELPER(target_ulong, do_rdhwr_cc, (target_ulong t0)) | ||
| 249 | -DEF_HELPER(target_ulong, do_rdhwr_ccres, (target_ulong t0)) | 246 | +DEF_HELPER(target_ulong, do_rdhwr_cpunum, (void)) |
| 247 | +DEF_HELPER(target_ulong, do_rdhwr_synci_step, (void)) | ||
| 248 | +DEF_HELPER(target_ulong, do_rdhwr_cc, (void)) | ||
| 249 | +DEF_HELPER(target_ulong, do_rdhwr_ccres, (void)) | ||
| 250 | DEF_HELPER(void, do_pmon, (int function)) | 250 | DEF_HELPER(void, do_pmon, (int function)) |
| 251 | DEF_HELPER(void, do_wait, (void)) | 251 | DEF_HELPER(void, do_wait, (void)) |
| 252 | 252 |
target-mips/op_helper.c
| @@ -1746,18 +1746,20 @@ void r4k_do_tlbr (void) | @@ -1746,18 +1746,20 @@ void r4k_do_tlbr (void) | ||
| 1746 | #endif /* !CONFIG_USER_ONLY */ | 1746 | #endif /* !CONFIG_USER_ONLY */ |
| 1747 | 1747 | ||
| 1748 | /* Specials */ | 1748 | /* Specials */ |
| 1749 | -target_ulong do_di (target_ulong t0) | 1749 | +target_ulong do_di (void) |
| 1750 | { | 1750 | { |
| 1751 | - t0 = env->CP0_Status; | 1751 | + target_ulong t0 = env->CP0_Status; |
| 1752 | + | ||
| 1752 | env->CP0_Status = t0 & ~(1 << CP0St_IE); | 1753 | env->CP0_Status = t0 & ~(1 << CP0St_IE); |
| 1753 | cpu_mips_update_irq(env); | 1754 | cpu_mips_update_irq(env); |
| 1754 | 1755 | ||
| 1755 | return t0; | 1756 | return t0; |
| 1756 | } | 1757 | } |
| 1757 | 1758 | ||
| 1758 | -target_ulong do_ei (target_ulong t0) | 1759 | +target_ulong do_ei (void) |
| 1759 | { | 1760 | { |
| 1760 | - t0 = env->CP0_Status; | 1761 | + target_ulong t0 = env->CP0_Status; |
| 1762 | + | ||
| 1761 | env->CP0_Status = t0 | (1 << CP0St_IE); | 1763 | env->CP0_Status = t0 | (1 << CP0St_IE); |
| 1762 | cpu_mips_update_irq(env); | 1764 | cpu_mips_update_irq(env); |
| 1763 | 1765 | ||
| @@ -1820,48 +1822,48 @@ void do_deret (void) | @@ -1820,48 +1822,48 @@ void do_deret (void) | ||
| 1820 | env->CP0_LLAddr = 1; | 1822 | env->CP0_LLAddr = 1; |
| 1821 | } | 1823 | } |
| 1822 | 1824 | ||
| 1823 | -target_ulong do_rdhwr_cpunum(target_ulong t0) | 1825 | +target_ulong do_rdhwr_cpunum(void) |
| 1824 | { | 1826 | { |
| 1825 | if ((env->hflags & MIPS_HFLAG_CP0) || | 1827 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1826 | (env->CP0_HWREna & (1 << 0))) | 1828 | (env->CP0_HWREna & (1 << 0))) |
| 1827 | - t0 = env->CP0_EBase & 0x3ff; | 1829 | + return env->CP0_EBase & 0x3ff; |
| 1828 | else | 1830 | else |
| 1829 | do_raise_exception(EXCP_RI); | 1831 | do_raise_exception(EXCP_RI); |
| 1830 | 1832 | ||
| 1831 | - return t0; | 1833 | + return 0; |
| 1832 | } | 1834 | } |
| 1833 | 1835 | ||
| 1834 | -target_ulong do_rdhwr_synci_step(target_ulong t0) | 1836 | +target_ulong do_rdhwr_synci_step(void) |
| 1835 | { | 1837 | { |
| 1836 | if ((env->hflags & MIPS_HFLAG_CP0) || | 1838 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1837 | (env->CP0_HWREna & (1 << 1))) | 1839 | (env->CP0_HWREna & (1 << 1))) |
| 1838 | - t0 = env->SYNCI_Step; | 1840 | + return env->SYNCI_Step; |
| 1839 | else | 1841 | else |
| 1840 | do_raise_exception(EXCP_RI); | 1842 | do_raise_exception(EXCP_RI); |
| 1841 | 1843 | ||
| 1842 | - return t0; | 1844 | + return 0; |
| 1843 | } | 1845 | } |
| 1844 | 1846 | ||
| 1845 | -target_ulong do_rdhwr_cc(target_ulong t0) | 1847 | +target_ulong do_rdhwr_cc(void) |
| 1846 | { | 1848 | { |
| 1847 | if ((env->hflags & MIPS_HFLAG_CP0) || | 1849 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1848 | (env->CP0_HWREna & (1 << 2))) | 1850 | (env->CP0_HWREna & (1 << 2))) |
| 1849 | - t0 = env->CP0_Count; | 1851 | + return env->CP0_Count; |
| 1850 | else | 1852 | else |
| 1851 | do_raise_exception(EXCP_RI); | 1853 | do_raise_exception(EXCP_RI); |
| 1852 | 1854 | ||
| 1853 | - return t0; | 1855 | + return 0; |
| 1854 | } | 1856 | } |
| 1855 | 1857 | ||
| 1856 | -target_ulong do_rdhwr_ccres(target_ulong t0) | 1858 | +target_ulong do_rdhwr_ccres(void) |
| 1857 | { | 1859 | { |
| 1858 | if ((env->hflags & MIPS_HFLAG_CP0) || | 1860 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1859 | (env->CP0_HWREna & (1 << 3))) | 1861 | (env->CP0_HWREna & (1 << 3))) |
| 1860 | - t0 = env->CCRes; | 1862 | + return env->CCRes; |
| 1861 | else | 1863 | else |
| 1862 | do_raise_exception(EXCP_RI); | 1864 | do_raise_exception(EXCP_RI); |
| 1863 | 1865 | ||
| 1864 | - return t0; | 1866 | + return 0; |
| 1865 | } | 1867 | } |
| 1866 | 1868 | ||
| 1867 | /* Bitfield operations. */ | 1869 | /* Bitfield operations. */ |
target-mips/translate.c
| @@ -7386,19 +7386,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx) | @@ -7386,19 +7386,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx) | ||
| 7386 | switch (rd) { | 7386 | switch (rd) { |
| 7387 | case 0: | 7387 | case 0: |
| 7388 | save_cpu_state(ctx, 1); | 7388 | save_cpu_state(ctx, 1); |
| 7389 | - tcg_gen_helper_1_1(do_rdhwr_cpunum, t0, t0); | 7389 | + tcg_gen_helper_1_0(do_rdhwr_cpunum, t0); |
| 7390 | break; | 7390 | break; |
| 7391 | case 1: | 7391 | case 1: |
| 7392 | save_cpu_state(ctx, 1); | 7392 | save_cpu_state(ctx, 1); |
| 7393 | - tcg_gen_helper_1_1(do_rdhwr_synci_step, t0, t0); | 7393 | + tcg_gen_helper_1_0(do_rdhwr_synci_step, t0); |
| 7394 | break; | 7394 | break; |
| 7395 | case 2: | 7395 | case 2: |
| 7396 | save_cpu_state(ctx, 1); | 7396 | save_cpu_state(ctx, 1); |
| 7397 | - tcg_gen_helper_1_1(do_rdhwr_cc, t0, t0); | 7397 | + tcg_gen_helper_1_0(do_rdhwr_cc, t0); |
| 7398 | break; | 7398 | break; |
| 7399 | case 3: | 7399 | case 3: |
| 7400 | save_cpu_state(ctx, 1); | 7400 | save_cpu_state(ctx, 1); |
| 7401 | - tcg_gen_helper_1_1(do_rdhwr_ccres, t0, t0); | 7401 | + tcg_gen_helper_1_0(do_rdhwr_ccres, t0); |
| 7402 | break; | 7402 | break; |
| 7403 | case 29: | 7403 | case 29: |
| 7404 | #if defined (CONFIG_USER_ONLY) | 7404 | #if defined (CONFIG_USER_ONLY) |
| @@ -7548,14 +7548,14 @@ static void decode_opc (CPUState *env, DisasContext *ctx) | @@ -7548,14 +7548,14 @@ static void decode_opc (CPUState *env, DisasContext *ctx) | ||
| 7548 | case OPC_DI: | 7548 | case OPC_DI: |
| 7549 | check_insn(env, ctx, ISA_MIPS32R2); | 7549 | check_insn(env, ctx, ISA_MIPS32R2); |
| 7550 | save_cpu_state(ctx, 1); | 7550 | save_cpu_state(ctx, 1); |
| 7551 | - tcg_gen_helper_1_1(do_di, t0, t0); | 7551 | + tcg_gen_helper_1_0(do_di, t0); |
| 7552 | /* Stop translation as we may have switched the execution mode */ | 7552 | /* Stop translation as we may have switched the execution mode */ |
| 7553 | ctx->bstate = BS_STOP; | 7553 | ctx->bstate = BS_STOP; |
| 7554 | break; | 7554 | break; |
| 7555 | case OPC_EI: | 7555 | case OPC_EI: |
| 7556 | check_insn(env, ctx, ISA_MIPS32R2); | 7556 | check_insn(env, ctx, ISA_MIPS32R2); |
| 7557 | save_cpu_state(ctx, 1); | 7557 | save_cpu_state(ctx, 1); |
| 7558 | - tcg_gen_helper_1_1(do_ei, t0, t0); | 7558 | + tcg_gen_helper_1_0(do_ei, t0); |
| 7559 | /* Stop translation as we may have switched the execution mode */ | 7559 | /* Stop translation as we may have switched the execution mode */ |
| 7560 | ctx->bstate = BS_STOP; | 7560 | ctx->bstate = BS_STOP; |
| 7561 | break; | 7561 | break; |