gwj / at91sam9263 · Commits

Commit 2784847001ba054a2912460f9735fd4497327d02

Authored by ths
1 parent b101234a

Un-break MIPS conditional moves, by Richard Sandiford. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4562 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 17 additions and 15 deletions
target-mips/translate.c
  View file @2784847
... ... @@ -5547,10 +5547,6 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5547 5547  
5548 5548 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5549 5549 {
5550   - TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
5551   - TCGv r_tmp = new_tmp();
5552   - TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
5553   - TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
5554 5550 int l1 = gen_new_label();
5555 5551 uint32_t ccbit;
5556 5552 TCGCond cond;
... ... @@ -5560,20 +5556,26 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5560 5556 else
5561 5557 ccbit = 1 << 23;
5562 5558 if (tf)
5563   - cond = TCG_COND_NE;
5564   - else
5565 5559 cond = TCG_COND_EQ;
  5560 + else
  5561 + cond = TCG_COND_NE;
  5562 +
  5563 + gen_load_gpr(cpu_T[0], rd);
  5564 + gen_load_gpr(cpu_T[1], rs);
  5565 + {
  5566 + TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
  5567 + TCGv r_tmp = new_tmp();
  5568 +
  5569 + tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
  5570 + tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
  5571 + tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
  5572 + tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
  5573 + dead_tmp(r_tmp);
  5574 + }
  5575 + tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
5566 5576  
5567   - gen_load_gpr(t0, rd);
5568   - gen_load_gpr(t1, rs);
5569   - tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
5570   - tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
5571   - tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
5572   - tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
5573   - tcg_gen_mov_tl(t0, t1);
5574 5577 gen_set_label(l1);
5575   - dead_tmp(r_tmp);
5576   - gen_store_gpr(t0, rd);
  5578 + gen_store_gpr(cpu_T[0], rd);
5577 5579 }
5578 5580  
5579 5581 #define GEN_MOVCF(fmt) \
... ...