gwj / at91sam9263 · Commits

Commit 269f3e95e8478bfa32ccfd96488341a90ec5e187

Authored by aurel32
1 parent 65d35a09

target-ppc: fix XER accesses on 64-bit targets 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5588 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 9 additions and 8 deletions
target-ppc/translate.c
  View file @269f3e9
... ... @@ -707,7 +707,8 @@ static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
707 707 {
708 708 int l1, l2, l3;
709 709  
710   - tcg_gen_shri_i32(cpu_crf[crf], cpu_xer, XER_SO);
  710 + tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
  711 + tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
711 712 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
712 713  
713 714 l1 = gen_new_label();
... ... @@ -1821,17 +1822,17 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1821 1822 tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);
1822 1823 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1823 1824 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1824   - tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
  1825 + tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1825 1826 tcg_gen_br(l2);
1826 1827 gen_set_label(l1);
1827   - tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
  1828 + tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1828 1829 gen_set_label(l2);
1829 1830 tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
1830 1831 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);
1831 1832 tcg_temp_free(temp);
1832 1833 } else {
1833 1834 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1834   - tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
  1835 + tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1835 1836 }
1836 1837 if (unlikely(Rc(ctx->opcode) != 0))
1837 1838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
... ... @@ -1901,15 +1902,15 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
1901 1902 temp = tcg_temp_new(TCG_TYPE_TL);
1902 1903 tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1903 1904 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
1904   - tcg_gen_ori_i32(cpu_xer, cpu_xer, 1 << XER_CA);
  1905 + tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1905 1906 tcg_gen_br(l2);
1906 1907 gen_set_label(l1);
1907   - tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
  1908 + tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1908 1909 gen_set_label(l2);
1909 1910 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1910 1911 } else {
1911 1912 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1912   - tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
  1913 + tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1913 1914 }
1914 1915 if (unlikely(Rc(ctx->opcode) != 0))
1915 1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
... ... @@ -3637,7 +3638,7 @@ GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3637 3638 {
3638 3639 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3639 3640 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3640   - tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
  3641 + tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3641 3642 }
3642 3643  
3643 3644 /* mfcr */
... ...